參數(shù)資料
型號(hào)： UDA1350ATS
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： IEC 958 audio DAC
中文描述： SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝： PLASTIC, SSOP-28
文件頁(yè)數(shù)： 8/32頁(yè)
文件大小： 124K
代理商： UDA1350ATS
2000 Mar 29
8
Philips Semiconductors
Preliminary specification
IEC 958 audio DAC
UDA1350ATS
8
FUNCTIONAL DESCRIPTION
The UDA1350ATS is a low cost audio IEC 958 decoder
with an on-board DAC. The minimum audio input sampling
frequency conforming to the IEC958 standard is 28.0 kHz
and the maximum audio sampling frequency is 54.0 kHz.
8.1
Clock regeneration and lock detection
The UDA1350ATS contains an on-board PLL for
regenerating a system clock from the IEC 958 input
bitstream.
When the on-board clock has locked to the incoming
frequency the lock indicator bit will be set and can be read
via the L3 interface. Internally the PLL lock indication is
combined with the PCM status bit of the input data stream.
When both the IEC 958 decoder and the on-board clock
have locked to the incoming signal and the input data
stream is PCM data, then pin LOCK will be asserted.
However, when the IC is locked but the PCM status bit
reports non-PCM data then pin LOCK is returned to LOW
level. The lock indication output can be used, for example,
for muting purposes.
8.2
Mute
The UDA1350ATS is equipped with a cosine roll-off mute
in the DSP data path of the DAC part. Muting the DAC, by
pin MUTE (in static mode) or via bit MT (in L3 mode) will
result in a soft mute as presented in Fig.3. The cosine
roll-off soft mute takes 32
×
32 samples = 24 ms at
44.1 kHz sampling frequency.
When operating in the L3 control mode the device will
mute on start-up. In L3 mode it is necessary to explicitly
switch off the mute for audio output by means of the MT bit
in the L3 register.
In the L3 mode pin MUTE does not have any function (the
same holds for several other pins) and can either be left
open-circuit (since it has an internal pull-down resistor) or
be connected to ground.
8.3
Auto mute
By default the outputs of the digital data output interface
and the DAC will be muted until the IC is locked,
regardless the level on pin MUTE (in static mode) or the
state of bit MT of the sound feature register (in L3 mode).
In this way only valid data will be passed to the outputs.
This mute is done in the SPDIF interface and is a hard
mute, not a cosine roll-off mute.
If needed this muting can be bypassed by setting
bit AutoMTtologic 0viatheL3 interface.Asaresultthe IC
will no longer mute during out-of-lock situations.
8.4
Data path
The UDA1350ATS data path consists of the IEC 958
decoder, the audio feature processor, digital interpolator
and noise shaper and the digital-to-analog converters.
8.4.1
IEC 958
INPUT
The UDA1350ATS IEC 958 decoder features an on-chip
amplifier with hysteresis which amplifies the IEC 958 input
signal to CMOS level (see Fig.4).
All 24 bits of data for left and right are extracted from the
input bitstream as well as several of the IEC 958 key
channel-status bits.
handbook, halfpage
mute
factor
0
10
5
15
25
0
0.8
MGU119
20
0.6
0.4
0.2
t (ms)
Fig.3 Mute as a function of raised cosine roll-off.
handbook, halfpage
MGS874
13
SPDIF
75
180 pF
10 nF
UDA1350ATS
Fig.4 IEC 958 input circuit and typical application.
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