參數(shù)資料
型號(hào): UDA1350ATS
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: IEC 958 audio DAC
中文描述: SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝: PLASTIC, SSOP-28
文件頁數(shù): 16/32頁
文件大小: 124K
代理商: UDA1350ATS
2
1
P
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8.6.7
O
VERVIEW OF
L3
INTERFACE REGISTERS
Table 9
UDA1350ATS register map
Notes
1.
2.
When writing new settings via the L3 interface, these bits should always remain logic 0 (default value) to warrant correct operation.
When writing new settings via the L3 interface, these bits should always remain logic 1 (default value) to warrant correct operation.
ADDR
FUNCTION
BIT
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Writable settings
00H
system
parameters
default
sound
features
default
volume
control DAC
default
multiplex
parameters
default
restore
L3 defaults
PON
1
M1
0
(1)
BB2
0
(1)
BB1
1
(2)
0
(1)
TR1
0
(1)
TR0
10H
M0
BB3
BB0
DE1
DE0
MT
0
0
0
0
0
0
0
VC4
0
VC3
0
VC2
0
VC1
1
VC0
11H
VC5
0
0
0
0
0
Auto
MT
1
0
RST
PLL
40H
0
(1)
0
(1)
0
(1)
0
(1)
7FH
Readable settings
18H
interpolator
parameters
SPDIF input
and lock
parameters
MT
stat
ACC0
38H
PLL
lock
SPD
lock
ASF1
ASF0
PCM
stat
PRE
ACC1
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