參數(shù)資料
型號(hào)： TWL1110GQE
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： PLASTIC, MICRO, BGA-80
文件頁(yè)數(shù)： 9/37頁(yè)
文件大?。?/td> 496K
代理商： TWL1110GQE
TWL1110
VOICE-BAND AUDIO PROCESSOR (VBAP
)
SLWS103 – NOVEMBER 2000
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless
otherwise noted) (continued)
power supply rejection and crosstalk attenuation
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply voltage rejection, transmit channel
MIC1N, MIC1P =0 V,
VDD = 3 Vdc + 100 mVpeak to peak, f = 0 to 50 kHz
– 86
–70
dB
Supply voltage rejection, receive channel,
EAR1 selected (differential)
PCM code = positive zero,
VDD = 3 Vdc + 100 mVpeak to peak, f = 0 to 50 kHz
– 98
–70
dB
Crosstalk attenuation, transmit-to-receive
(differential)
MIC1N, MIC1P = 0 dB, f = 300 to 3400 Hz measured
differentially between EAR1ON and EAR1OP
70
dB
Crosstalk attenuation, receive-to-transmit
PCMIN = 0 dBm0, f = 300 to 3400 Hz measured at
PCMO, EAR1 amplifier
70
dB
switching characteristics
clock timing requirements for 2.048-MHz CLK
PARAMETER
MIN
NOM
MAX
UNIT
tt
Transition time, MCLK
10
ns
f(mclk)
MCLK frequency
2.048
MHz
MCLK jitter
37%
Number of PCMCLK clock cycles per PCMSYN frame
256
tc(PCMCLK) PCMCLK clock period
156
488
512
ns
Duty cycle, PCMCLK
45%
50%
68%
transmit timing requirements for 2.048-MHz CLK (see Figure 8)
PARAMETER
MIN
MAX
UNIT
tsu(PCMSYN)
Setup time, PCMSYN high before falling edge of PCMCLK
20
tc(PCMCLK)–20
ns
th(PCMSYN)
Hold time, PCMSYN high after falling edge of PCMCLK
20
tc(PCMCLK)–20
ns
receive timing requirements for 2.048-MHz CLK (see Figure 9)
PARAMETER
MIN
MAX
UNIT
tsu(PCSYN)
Setup time, PCMSYN high before falling edge of PCMCLK
20
tc(PCMCLK)–20
ns
th(PCSYN)
Hold time, PCMSYN high after falling edge of PCMCLK
20
tc(PCMCLK)–20
ns
tsu(PCMI)
Setup time, PCMI high or low before falling edge of PCMCLK
20
ns
th(PCMI)
Hold time, PCMI high or low after falling edge of PCMCLK
20
ns
clock timing requirements for 128-kHz CLK
PARAMETER
MIN
NOM
MAX
UNIT
tt
Transition time, MCLK
10
ns
f(mclk)
MCLK frequency
128
kHz
MCLK jitter
5%
Number of PCMCLK clock cycles per PCMSYN frame
16
tc(PCMCLK) PCMCLK clock period
742.19
781.25
820.31
ns
Duty cycle, PCMCLK
40%
50%
60%
tc(PCMSYN) PCMSYN clock period
125
s
Duty cycle, PCMCLK
49.5%
50%
50.5%
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