TWL1110
VOICE-BAND AUDIO PROCESSOR (VBAP
)
SLWS103 – NOVEMBER 2000
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics (continued)
transmit timing requirements for 128-kHz CLK (see Figure 12)
PARAMETER
MIN
MAX
UNIT
tsu(PCMSYN)
Setup time, PCMSYN high before rising edge of PCMCLK
20
tc(PCMCLK)/4
ns
th(PCMSYN)
Hold time, PCMSYN high after falling edge of PCMCLK
20
tc(PCMCLK)/4
ns
tv(PCMO)
Data valid time after the rising edge of PCMSYNC
50
ns
receive timing requirements for 128-kHz CLK (see Figure 11)
PARAMETER
MIN
MAX
UNIT
tsu(PCSYN)
Setup time, PCMSYN high before rising edge of PCMCLK
20
tc(PCMCLK)/4
ns
th(PCSYN)
Hold time, PCMSYN high after falling edge of PCMCLK
20
tc(PCMCLK)/4
ns
tsu(PCMI)
Setup time, PCMI high or low before falling edge of PCMCLK
20
ns
th(PCMI)
Hold time, PCMI high or low after falling edge of PCMCLK
20
ns
propagation delay times, CLmax = 10 pF (see Figure 8)
PARAMETER
MIN
MAX
UNIT
tpd1
From PCMCLK bit 1 high to PCMO bit 1 valid
35
ns
tpd2
From PCMCLK high to PCMO valid, bits 2 to n
35
ns
tpd3
From PCMCLK bit n low to PCMO bit n Hi-Z
30
ns
I2C bus timing requirements (see Figure 10)
PARAMETER
MIN
MAX
UNIT
SCL
Clock frequency
400
kHz
t(HIGH)
Clock high time
600
ns
t(LOW)
Clock low time
1300
ns
th(STA)
Hold time (repeated) START condition. After this period the first clock pulse is generated.
600
ns
tsu(STA)
Setup time for repeated START condition
600
ns
th(DAT)
Data input hold time
0
ns
tsu(DAT)
Data input setup time
100
ns
tsu(STO)
STOP condition setup time
600
ns
t(BUF)
Bus free time
1300
ns
tr
SDA and SCL rise time
300
ns
tf
SDA and SCL fall time
300
ns
DTMF generator characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DTMF high to low tone relative amplitude (pre-emphasis)
1.5
2
2.5
dB
Tone frequency accuracy (for DTMF)
Resolution of 7.8125 Hz
–1.5
1.5
%
Harmonic distortion
Measured from lower tone group to
highest parasitic
–20
dB
MICBIAS characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Load impedance (bias mode)
5
k