參數(shù)資料
型號(hào)： TVP5022
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP80
封裝： POWER, PLASTIC, TQFP-80
文件頁(yè)數(shù)： 6/91頁(yè)
文件大小： 411K
代理商： TVP5022
1–4
1.5
Terminal Functions
TERMINAL
I/O
DESCRIPTIONS
NAME
NO.
I/O
DESCRIPTIONS
Analog video
VI_1A
VI_1B
VI_2A
VI_2B
5
4
10
11
I
Analog video inputs. Up to four composite inputs or two S-video inputs or a
combination of the two. The inputs must be AC coupled. The recommended coupling
capacitor is 0.1
F.
Clock Signals
PCLK
40
O
Pixel clock output. The frequency is 12.2727 MHz for square-pixel NTSC,
14.75 MHz for square-pixel PAL, and 13.5 MHz for ITU-R BT.601 sampling modes.
PREF
39
O
Clock phase reference signal. This signal qualifies clock edges when SCLK is used
to clock data that is changing at the pixel clock rate.
SCLK
38
O
System clock output with twice the frequency of the pixel clock (PCLK).
XTAL1
XTAL2
35
36
I
External clock reference. The user may connect XTAL1 to a TTL-compatible
oscillator or to one terminal of a crystal oscillator. The user may connect XTAL2 to the
other terminal of the crystal oscillator or not connect XTAL2 at all. Square pixel
sampling uses an oscillator frequency of 26.800 MHz. ITU-R BT.601 sampling uses
an oscillator frequency of 24.576 MHz.
Digital Video
EXT_DATA_8
61
I
Bit [8] of a 9-or 10-bit digital composite video input
UV[0:7]
51, 52,
53, 55,
56, 58,
59, 60
I/O
Digital chrominance outputs. These terminals may be configured to output data from
the channel 2 A/D converter. A vendor modifiable subsystem ID may be initialized by
configuring the UV [7:0] terminals with pull-up/pull-down resistors.
Y[0:7]
41, 42,
43, 45,
46, 48,
49, 50
O
Digital luminance outputs, or multiplexed luminance and chrominance outputs.
These terminals may be configured to output data from the channel 1 A/D converter.
HOST PORT-bus
VMI
I2C
VIP
A[0:1]
73, 74
I
VMI address port
D[0:7]
63, 64
66, 67
69, 70
71, 72
I/O
VMI data port – bit [7:0].
INTREQ
80
O
Interrupt request
(INTREQ)
Interrupt request (VIRQ)
VC0
79
I/O
VMI port data ack. or
ready signal (DTACK)
Serial clock (SCL)
Hardware address
bit-0 (HAD[0])
VC1
78
I/O
VMI Port Read-Write or
Write (RW/WR)
Serial data (SDA)
Hardware address bit-1
HAD[1]
VC2
77
I/O
VMI port data strobe or
read signal (DS/RD)
Hardware control
(HCTL)
VC3
76
I
VMI port chip select. (VC)
Slave address select
(I2CA)
VIPCLK
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