參數(shù)資料
型號(hào)： TVP5022
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP80
封裝： POWER, PLASTIC, TQFP-80
文件頁(yè)數(shù)： 31/91頁(yè)
文件大小： 411K
代理商： TVP5022
2–21
2.7.1
VIP Host Port Terminal Description
Table 2–4. VIP Host Port Terminal Description
SIGNAL
TYPE
DESCRIPTION
VC3 (VIPCLK)
I
VIP Host clock (25 MHz – 33 MHz)
VC0 VC1 (HAD[0:1])
I/O
Host address/data bus
VC0 = (HAD_0)
VC1 = (HAD_1)
VC2 (HCTL)
I/O (OD)
Host control: This includes the symbolic signals of VFRAME, DTACK, and VSTOP
INTREQ (VIRQ#)
O (OD)
Interrupt request. Shared signal with VDP
VC3 (VIPCLK) is the host port clock, operating from 25 MHz–33 MHz. VIPCLK can come from any source.
VC0 and VC1 (HAD[0:1]) is a two-wire bus that transfers commands, addresses, and data between master
and slave devices.
VC2 (HCTL) is a shared control terminal. The master drives it to initiate and terminate data transfers. The
slave drives it to terminate and add wait states to data transfers. Because VC2 is a shared control signal,
special attention must be given to its generation to avoid bus conflicts.
INTREQ is a normally open drain pin that signals interrupts to the host controller. Using the interrupt
configuration register at subaddress C2, this terminal can be configured as a conventional CMOS I/O buffer
(non-open drain). Conflict is possible if multiple devices are connected to the INTREQ signal when it is
configured in non-open drain mode.
2.7.2
VIP Phases
Command Phase
Address Phase
DC
Retry Phase
Data Phase
TAPh
Command
Address
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
Don’t
Care
Don’t
Care
Don’t
Care
Don’t
Care
Don’t
Care
7:6
5:4
3:2
1:0
7:6
Data
Decode Phase Allows
Slave to Decode
Address
Bus Turn Around Phase
Cmd
Master Drive HCTL High
to Start Transfer
Slave Drives DTACK to
Signal Data is Ready for
the Next Phase
GUI Must Drive This
Low Dring Idle
Master Drives Low
During Idle
Master 3-states
VC2 (HCTL) Floats
VSTOP Can Drive Low to
Terminate The Transfer. If Terminated
There Will Be No Data Phase
Slave Drives High if
Not Terminated in
Cycle
Slave 3-states
VC2 (HCTL) Remains High
FRAME and or VSTOP Drives
Low to Terminate The Transfer
Slave May Drive DTACK Low For
The Next Byte. It is Irrelevant as
Transfer is Already Terminated
VC3
(VIPCLK)
VC0 (HAD0)
VC1 (HAD1)
VC2
(HCTL)
Zero Wait State
Figure 2–21. VIP Transfer Example
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