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參數(shù)資料
| 型號： | TVP5022 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 42/91頁 |
| 文件大?。?/td> | 411K |
| 代理商： | TVP5022 |
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2–31
VBI FIFO:
The VBI FIFO containing sliced VBI data is directly readable by the VMI host.
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Read VBI FIFO
1
0
Data from FIFO
Status/Interrupt Register:
The status/interrupt register provides the host with information containing the source of an interrupt. After
an interrupt condition is set, the condition can be reset by writing a one to the appropriate bit in the
status/interrupt register.
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Access status/interrupt register
1
Data to/from status/interrupt register
2.11.2
VMI Microcode Write Operation
Data written to indirect register 7E will be written to the TVP5022 program RAM. During the address write
cycle the microprocessor resets and points to location zero in the program and remains reset. The
microprocessor requires a clear-reset operation upon completion of the write operation. The host performs
the reset by writing into the 7F register to clear reset and resume microprocessor function. (There is no
specific data to be written into the 7F register; any data will resume microprocessor function).
To avoid violating VMI cycle time requirements during microcode write operation, the host can poll the cycle
complete bit in the VMI status register after writing each byte of data to the VMI data register. Alternatively,
the cycle complete enable bit in the interrupt enable register (indirect address C1) can be set to generate
an interrupt for the host when a write operation is complete.
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write microcode
Register address
0
1
0
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write microcode
Register data
Write microcode
Register Data
Write microcode
Register data
0
1
First byte of microcode data
(Wait for cycle complete status or interrupt)
Second Byte of microcode data
(Wait for cycle complete status or interrupt)
Last byte of microcode data
(Wait for cycle complete status or interrupt)
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write clear reset
Register address
0
1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write clear reset
Dummy data
0
1
X
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP5031 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL VIDEO DECODER |
| TVP5031CPFP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Color Decoder Circuit |
| TVP5031PFP | 功能描述:IC 9-BIT VIDEO DECODER 80-QFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| TVP5031TQFP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL VIDEO DECODER |
| TVP5040 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL Digital Video Decoder With Macrovision Detection |
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