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參數(shù)資料
| 型號： | TVP5022 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 32/91頁 |
| 文件大小： | 411K |
| 代理商： | TVP5022 |
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2–22
Table 2–5. VIP Host Port Phase Description
PHASE
EXPLANATION
Command
All host port transfers start with a command phase. The 8-bit command/address byte is multiplexed onto
VC0 and VC1 (HAD[1:0]) during the command phase. The command byte selects between devices, read,
and write cycles, register or FIFO transfers, and contains the most significant four bits of the register
address.
Address
During register transfers the command phase is followed by the address extension phase. The least
significant 8-bits of the VIP register address are multiplexed onto VC0 and VC1 (HAD[1:0]) during the
address extension phase. This phase is not present during FIFO transfers.
Decode
Following the command or command/address phase(s), the bus requires one clock delay to allow slave
devices to decode the address and determine if they are able to respond within the 1 wait phase
requirement for active operation.
Retry
The four clock cycles immediately following the decode phase constitute the retry phase. During the retry
phase, the slave indicates its desire to terminate the operation without transferring any data (retry), add a
wait phase or transfer the first byte of data. When the slave asserts VSTOP, the transfer ends with the retry
phase. When the slave neither terminates the transfer nor accepts the byte, the retry phase is followed by
a wait phase.
Wait
During the second cycle of a decode, retry or wait phase, the slave indicates its ability to transfer the next
byte of data by driving VC2 (HCTL) low. When the slave does not drive VC2 (HCTL) low and the transfer is
not terminated, the current phase is followed by a wait phase. During wait phases, the current owner
(master for writes, slave for reads) continues to drive the HAD bus, but no data is transferred. The slave is
allowed to add one wait phase per byte to register accesses without compromising system timing.
Additional wait phases are not prevented but overall system reliability may be compromised.
Data
When VC2 (HCTL) is removed during cycle 1 of a retry, wait or data phase, a data phase follows the
current phase. The bus transfers data between master and slave devices during data phases. The data is
multiplexed onto VC0 and VC1 (HAD[1:0]).
TA
Immediately following the last transfer phase of a read transfer, the slave requires a one cycle delay giving
time to 3-state the VC0 and VC1 (HAD) bus. The master is free to begin a new bus transfer, driving VC0
and VC1 (HAD) and VC2 (HCTL) immediately following the TA phase.
Table 2–6. Condensed Table Command/Address
COMMAND
Cmd/Addr
REGISTER ADDRESS
DATA
COMMENT
[7:4]
[3:0]
[7:0]
01
0/1
0
0000
00000000 thru 11111111
dddddddd
VIP configuration registers
01
0/1
0
0001
00000000 thru 11111111
dddddddd
General TVP registers
01
1
0
0010
00000000 thru 11111111
xxxxxxxx
No latency read access 1 phase
01
1
0
0011
addr as prev. written
ddddddd
No latency read access 2 phase
01
1
0000
No addr phase
xxx0/1xxx0/1
FIFO status 0 read
01
1
0001
No addr phase
xxxxxx11
FIFO status 1 read
01
1
0100
No addr phase
dddddddd
FIFO VBI data read
2.7.3
Command Byte
During the command byte phase, the hardware control line (VC2) will transition high and the hardware
address lines (VC0 and VC1) transmits the command byte from the host to the TVP5022. The command
byte determines the nature of the data transfer and the affected TVP5022 address space.
7
6
5
4
3
2
1
0
Command
DEVSEL1 (0)
DEVSEL0 (1)
R/W
F/R
A11
A10
A9
A8
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