參數(shù)資料
型號: TVP5020CPFP
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PQFP80
封裝: POWERPAD, PLASTIC, HTQFP-80
文件頁數(shù): 75/87頁
文件大小: 394K
代理商: TVP5020CPFP
2–63
2.15.42 Interrupt Enable Register
VIP address
1C1
VMI address
C1
I2C address
C1
7
6
5
4
3
2
1
0
Reserved
tvpLock
Interrupt
Enable
Cycle
Complete
Enable
Bus Error
Enable
CC Odd
Field Enable
CC Even
Field Enable
Teletext
Threshold
Enable
Teletext
Data Enable
The interrupt enable register is used by the external processor to mask unnecessary interrupt sources. Bits
loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the external terminal.
Conversely, bits loaded with a 0 mask the corresponding interrupt condition from generating an interrupt on
the external terminal. This register only affects the external terminal, it does not affect the bits in the interrupt
status register. A given condition can set the appropriate bit in the status register and not cause an interrupt
on the external terminal. To determine if this device is driving the interrupt terminal, check either the interrupt
status register with the interrupt enable register or check the state of the interrupt bit in the interrupt
configuration register.
2.15.43 Interrupt Configuration Register
VIP address
1C2
VMI address
C2
I2C address
C2
7
6
5
4
3
2
1
0
Reserved
YUV output enable
Interrupt
Interrupt polarity
Interrupt Polarity
0 = Interrupt is active low.
1 = Interrupt is active high.
Interrupt
0 = Interrupt terminal is not
active.
1 = Interrupt terminal is active.
Reflects state of interrupt
terminal.
YUV output
enable
0 = YUV terminals are high
impedance.
1 = YUV terminals are active.
The interrupt configuration register configures the polarity of the external interrupt terminal.
2.15.44 Interrupt Status Register
VIP address
NA
VMI address
11 (direct)
I2C address
NA
The status register is a duplicate of the interrupt status register at subaddress C0h.
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