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參數(shù)資料
| 型號： | TVP5020CPFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWERPAD, PLASTIC, HTQFP-80 |
| 文件頁數(shù)： | 38/87頁 |
| 文件大?。?/td> | 394K |
| 代理商： | TVP5020CPFP |
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2–29
2.11.1
VMI Register Mapping
The VMI module contains only four registers that are accessible by the host. The address register holds an
indirect address for internal register access. When the host accesses the data register, the VMI module
reads or writes the internal register selected by the indirect address register.
Two other registers are provided for direct access. The FIFO register provides direct access to the VBI FIFO
and the second direct access register is the status/interrupt register. This register contains the state of the
interrupt sources.
A[1:0]
00
Address register
01
Data register
10
FIFO
11
Status register
Figure 2–29. VMI Address Register Map
Normally, read or write operations require two accesses. To read the FIFO register, set A[1:0] to 10(binary)
and perform a read cycle. The FIFO read data will be placed on the D[7:0] bus. To read/write the
status/interrupt register, set A[1:0] to 11(binary) and perform a read/write cycle. The read/write will be muxed
appropriately to/from the external data bus.
Indirect Register Read/Write:
All VMI accesses except for the VBI FIFO and the status/interrupt register require a two-step operation. To
access an indirect register, write the internal address to the VMI address register. The first step requires
setting A[1:0] to 00 and performing a write cycle with D[7:0] equaling the indirect address. To write to an
indirect register, the second step is to write the data to VMI address 01. To read an indirect register, the
second step is to read the the requested data from address 01.
Read the indirect register
STEP 1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write register address
0
Register address
STEP 2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Read register data
0
1
Data from register
Write to the indirect register
STEP 1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write register address
0
Register address
STEP 2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write register data
0
1
Data to register
Latency:
VMI access to indirect addresses 00–8F requires special consideration due to response latencies of up to
64
s for these addresses. Latency occurs between steps one and two for a read operation and following
step two of a write operation. To avoid violating the VMI cycle time requirements, the host can poll the cycle
complete bit in the VMI status register following step one for a read or step two for a write. Alternatively, the
cycle complete enable bit in the interrupt enable register (indirect address C1) can be set to generate an
interrupt for the host when access is complete.
VMI access to indirect addresses 90-CF occur with minimal latency. Interrupts will not be generated for the
completion of access cycles to these addresses.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP5020PFC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| TVP5020TQFP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL VIDEO DECODER |
| TVP5021PFP | 功能描述:視頻 IC NTSC/PAL DIGITAL VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5021PFPG4 | 功能描述:視頻 IC NTSC/PAL DIGITAL VIDEO DECODER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TVP5031 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL VIDEO DECODER |
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