![](http://datasheet.mmic.net.cn/130000/TVP5020CPFP_datasheet_5023352/TVP5020CPFP_40.png)
2–26
2.7.4
VIP Microcode Write Operation
Data is written to the TVP5020 program RAM during the microcode write operation. During the write cycle,
the microprocessor resets and points to location zero in the program and remains reset. Following the first
data phase, the data phase is repeated until all microcode is written. The microprocessor requires a
clear-reset operation upon completion of the write operation. The host performs the reset by writing into the
7F register to clear reset and resume microprocessor function. (There is no specific data to be written into
the 7F register; any data will resume microprocessor function).
COMMAND PHASE
ADDRESS PHASE
DATA PHASE
(to TVP5020)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Microcode write
0
1
0
1
0
1
0 D D D D D D D D
The data phase is repeated to the end of the microcode.
COMMAND PHASE
ADDRESS PHASE
DATA PHASE
(to TVP5020)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Clear reset
0
1
0
1
0
1
1 X X X X X X X X
2.7.5
VIP Microcode Read Operation
Data is read from the TVP5020 program RAM during the microcode read operation. During the read cycle,
the microprocessor resets and points to location zero in the program and remains reset. Following the first
data phase, the data phase is repeated until all microcode is read. The microprocessor requires a clear-reset
operation upon completion of the read operation. The host performs the reset by writing into the 7F register
to clear reset and resume microprocessor function. (There is no specific data to be written into the 7F
register; any data will resume microprocessor function).
COMMAND PHASE
ADDRESS PHASE
DATA PHASE
(from TVP5020)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Microcode read
0
1
0
1
0
1
0 D D D D D D D D
The data phase is repeated to the end of the microcode.
COMMAND PHASE
ADDRESS PHASE
DATA PHASE
(to TVP5020)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Clear reset
0
1
0
1
0
1
1 X X X X X X X X
2.8
Video Module Interface (VMI) Host Interface
The VMI host port interface is configurable for three possible modes of operation. The mode of operation
is determined by attaching pullup or pulldown resistors to the GLCO, PALI, and FID terminals. Table 2–7
shows the various modes. (0=pulldown and 1=pullup)
Table 2–7. VMI Host Port Select
TERMINALS
GLCO
PALI
FID
TERMINALS
2
1
0
VMI Host Port Mode A
1
0
1
VMI Host Port Mode B
1
0
VMI Host Port Mode C
1