參數(shù)資料
型號: TSC21020F-20SCHXXX
廠商: ATMEL CORP
元件分類: 數(shù)字信號處理外設(shè)
英文描述: 40-BIT, DSP-FLOATING POINT PROCESSOR, UUC
封裝: DIE
文件頁數(shù): 4/37頁
文件大?。?/td> 483K
代理商: TSC21020F-20SCHXXX
TSC21020F
Rev. E – Oct. 05, 1998
12
Table 1 : Syntax Notation Conventions
Notation
Meaning
UPPERCASE
Explicit syntax – assembler keyword (notation only ;
assembler is not case-sensitive and lowercase is
the preferred programming convention)
;
Instruction terminator
,
Separates parallel operations in an instruction
italics
Optional part of instruction
between lines List of options (choose one)
<datan>
n-bit immediate data value
<addrn>
n-bit immediate address value
<reladdrn>
n-bit immediate PC-relative address value
compute
ALU, multiplier, shifter or multifunction
operation (from Tables 4-7)
shiftimm
Shifter immediate operation (from Table 6)
condition
Status condition (from Table 2)
termination
Termination condition (from Table 2)
ureg
Universal register (from Table 3)
sreg
System register (from Table 3)
dreg
R15-R0, F15-F0 ; register file location
Ia
I7-I0 ; DAG1 index register
Mb
M7-M0 ; DAG1 modify register
Ic
I15-I8 ; DAG2 index register
Md
M15-M8 ; DAG2 modify register
Table 2 : Condition and Termination Codes
Name
Description
eq
ALU equal to zero
ne
ALU not equal to zero
ge
ALU greater than or equal to zero
lt
ALU less than zero
le
ALU less than or equal to zero
gt
ALU greater than zero
ac
ALU carry
not ac
Not ALU carry
av
ALU overflow
not av
Not ALU overflow
mv
Multiplier overflow
not mv
Not multiplier overflow
ms
Multiplier sign
not ms
Not multiplier sign
sv
Shifter overflow
not sv
Not shifter overflow
sz
Shifter zero
not sz
Not shifter zero
flag0_in
Flag 0
not flag0_in
Not Flag 0
flag1_in
Flag 1
not flag1_in
Not Flag 1
flag2_in
Flag 2
not flag2_in
Not Flag 2
flag3_in
Flag 3
not flag3_in
Not Flag 3
tf
Bit test flag
not tf
Not bit test flag
lce
Loop counter expired (DO UNTIL)
not lce
Loop counter not expired (IF)
forever
Always False (DO UNTIL)
true
Always True (IF)
In a conditional instruction, the execution of the entire instruction is
based on the specified condition.
Table 3 : Universal Registers
Name
Function
Register file
R15-R0
Register file locations
Program Sequencer
PC*
Program counter ; address of instruction currently
executing
PCSTK
Top of PC stack
PCSTKP
PC stack pointer
FADDR*
Fetch address
DADDR*
Decode address
LADDR
Loop termination address, code ; top of loop
address stack
CURLCNTR
Current loop counter ; top of loop count stack
LCNTR
Loop count for next nested counter-controlled loop
Data Address Generators
I7-I0
DAG1 index registers
M7-M0
DAG1 modify registers
L7-L0
DAG1 length registers
B7-B0
DAG1 base registers
I15-I8
DAG2 index registers
M15-M8
DAG2 modify registers
L15-L8
DAG2 length registers
B15-B8
DAG2 base registers
Bus Exchange
PX1
PMD-DMD bus exchange 1 (16 bits)
PX2
PMD-DMD bus exchange 2 (32 bits)
PX
48-bit PX1 and PX2 combination
Timer
TPERIOD
Timer period
TCOUNT
Timer counter
Memory Interface
DMWAIT
Wait state and page size control for data memory
DMBANK1
Data memory bank 1 upper boundary
DMBANK2
Data memory bank 2 upper boundary
DMBANK3
Data memory bank 3 upper boundary
DMADR*
Copy of last data memory address
PMWAIT
Wait state and page size control for program
memory
PMBANK1
Program memory bank 1 upper boundary
PMADR*
Copy of last program memory address
System Register
MODE1
Mode control bits for bit-reverse, alternate
registers, interrupt nesting and enable, ALU
saturation, floating-point rounding mode and
boundary
MODE2
Mode control bits for interrupt sensitivity, cache
disable and freeze, timer enable, and I/O flag
configuration
IRPTL
Interrupt latch
IMASK
Interrupt mask
IMASKP
Interrupt mask pointer (for nesting)
ASTAT
Arithmetic status flags, bit test, I/O flag values, and
compare accumulator
STKY
Sticky arithmetic status flags, circular buffer
overflow flags, stack status flags (not sticky)
USTAT1
User status register 1
USTAT2
User status register 2
* read-only
Refer to User’s Manual for bit-level definitions of each register.
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