參數(shù)資料
型號: TSC21020F-20SCHXXX
廠商: ATMEL CORP
元件分類: 數(shù)字信號處理外設(shè)
英文描述: 40-BIT, DSP-FLOATING POINT PROCESSOR, UUC
封裝: DIE
文件頁數(shù): 10/37頁
文件大小: 483K
代理商: TSC21020F-20SCHXXX
TSC21020F
Rev. E – Oct. 05, 1998
18
Reset
Parameter
20 MHz
Frequency
Dependency*
Unit
Parameter
Min
Max
Min
Max
Unit
Timing Requirement
tWRST1 RESET Width Low
200
4tCK
ns
tSRST2 RESET Setup before CLKIN High
29
50
29 + DT/2
30
ns
NOTES
*
DT = tCK – 50 ns
1.
Applies after the power-up sequence is complete. At power up, the Internal Phase Locked Loop requires no more than 1000 CLKIN cycles
while RESET is low, assuming stable VDD and CLKIN (not including clock oscillator start-up time).
2.
Specification only applies in cases where multiple TSC21020F processors are required to execute in program counter lock-step (all
processors start execution at location 8 in the same cycle). See the Hardware Configuration chapter of the ADSP-21020 User’s Manual from
Analog Devices for reset sequence information.
Figure 4. Reset
Interrupts
Parameter
20 MHz
Frequency
Dependency*
Unit
Min
Timing Requireent
tSIR
IRQ3-0 Setup before CLKIN High
38
38 + 3DT/4
ns
tHIR
IRQ3-0 Hold after CLKIN High
0
ns
tIPW
IRQ3-0 Pulse Width
55
tCK + 5
ns
NOTES
*
DT = tCK – 50 ns
Meeting setup and hold guarantees interrupts will be latched in that cycle. Meeting the pulse width is not necessary if the setup and hold is met.
Likewise, meeting the setup and hold is not necessary if the pulse width is met. See the Hardware Configuration chapter of the ADSP-21020
User’s Manual from Analog Devices for interrupt servicing information.
Figure 5. Interrupts
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