參數(shù)資料
型號(hào)： TSC21020F-20SCHXXX
廠商： ATMEL CORP
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： 40-BIT, DSP-FLOATING POINT PROCESSOR, UUC
封裝： DIE
文件頁(yè)數(shù)： 35/37頁(yè)
文件大?。?/td> 483K
代理商： TSC21020F-20SCHXXX
TSC21020F
Rev. E – Oct. 05, 1998
7
An interrupt can occur at any time while the TSC21020F
is executing a program. Internal events that generate
interrupts include arithmetic exceptions, which allow for
fast trap handling and recovery.
Timer
The programmable interval timer provides periodic
interrupt
generation.
When
enabled,
the
timer
decrements a 32-bit count register every cycle. When this
count register reaches zero, the TSC21020F generates an
interrupt and asserts its TIMEXP output. The count
register is automatically reloaded from a 32-bit period
register and the count resumes immediately.
System Interface
Figure 2 shows an TSC21020F basic system configuration.
The external memory interface supports memory-
mapped
peripherals
and
slower
memory
with
a
user-defined combination of programmable wait states
and hardware acknowledge signals. Both the program
memory and data memory interfaces support addressing
of page-mode DRAMs.
The TSC21020F’s internal functions are supported by
four internal buses : the program memory address (PMA)
and data memory address (DMA) buses are used for
addresses associated with program and data memory. The
program memory data (PMD) and data memory data
(DMD) buses are used for data associated with the two
memory spaces. These buses are extended off chip. Four
data memory select (DMS) signals select one of four
user-configurable banks of data memory. Similarly, two
program memory select (PMS) signals select between
two user-configurable banks of program memory. All
banks are independently programmable for 0-7 wait
states.
The PX registers permit passing data between program
memory and data memory spaces. They provide a bridge
between the 48-bit PMD bus and the 40-bit DMD bus or
between the 40-bit register file and the PMD bus.
The PMA bus is 24 bits wide allowing direct access of up
to 16M words of mixed instruction code and data. The
PMD is 48 bits wide to accommodate the 48-bit
instruction width. For access of 40-bit data the lower 8
bits are unused. For access of 32-bit data the lower 16 bits
are ignored.
The DMA bus is 32 bits wide allowing direct access of up
to 4 Gigawords of data. The DMD bus is 40 bits wide. For
32-bit data, the lower 8 bits are unused. The DMD bus
provides a path for the contents of any register in the
processor to be transferred to any other register or to any
external data memory location in a single cycle. The data
memory address comes from one of two sources : an
absolute value specified in the instruction code (direct
addressing) or the output of a data address generator
(indirect addressing).
Figure 2. Basic System Configuration.
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