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參數(shù)資料
| 型號(hào)： | TRCV0110G |
| 廠商： | Lineage Power |
| 英文描述： | 10 Gbits/s Clock Recovery, 1:16 Data Multiplexer(10 G位/秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)多路復(fù)用器) |
| 中文描述： | 10 Gb /秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)復(fù)用器（10政位/秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)多路復(fù)用器） |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 524K |
| 代理商： | TRCV0110G |
Advance Data Sheet
August 2000
TRCV0110G
10 Gbits/s Clock Recovery, 1:16 Data Demultiplexer
9
Lucent Technologies Inc.
Pin Information
(continued)
Table 3. Pin Descriptions—622.08 Mbits/s and Related Signals
(continued)
* Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
I = input, O = output. I
u
= an internal pull-up resistor on this pin, I
d
= an internal pull-down resistor on this pin, I
t
= an internal termination
resistance of 50
on this pin.
Pin
B1
Symbol
*
MUTEDMXN
Type
I
u
Level
CMOS
Name/Description
Mute DeMUX Parallel Output Data (Active-Low).
Forces
all demultiplexer output data D[15:0] to a logic-low level.
0 = Demultiplexer output muted
1 or no connection = normal operation
Recovered Clock Output (622 MHz).
622 MHz recovered
differential clock output. Pins are active but forced to
differential logic low when MUTE622N = 0. Note that this
clock frequency will scale by 15/14 when operating at the
FEC rate.
Mute CK622P/N Clock Output (Active-Low).
Forces
CK622P/N to logic low when MUTE622N is active.
0 = muted
1 or no connection = enabled
Recovered Clock Output (155 MHz or 622 MHz).
Selectable 155 MHz or 622 MHz recovered differential
clock output. Pins are active but forced to differential logic
low when MUTECKON = 0. Note that these clock
frequencies will scale by 15/14 when operating at the FEC
rate. Use the FREQCKO pin to select the frequency.
CKO Frequency Select.
Selects 155 MHz or 622 MHz
clock frequency on CLKOP/N.
0 = 155 MHz CKOP/N
1 or no connection = 622 MHz CKOP/N
Mute CKOP/N Clock Output (Active-Low).
Forces CKOP/
N to logic low when MUTECKON is active.
0 = muted
1 or no connection = enabled
Reference Clock Input (155 MHz, or 622 MHz).
Note that this clock frequency must scale by 15/14 when
operating the device at the FEC rate.
Reference Frequency Select.
Sets CDR PLL to accept
155 MHz, or 622 MHz reference frequency on REFCLKP/N.
0 = 155 MHz REFCLKP/N
1 or no connection = 622 MHz REFCLKP/N
Resistor Reference LVDS.
LVDS bias reference resistor.
Connect a
TBD
k
resistor to V
CCD
.
Amplifier Common Mode.
Input amplifier common bias
point. Place a 0.047
μ
F RF bypass capacitor to GND.
P11
N11
CK622P
CK622N
O
LVDS
B5
MUTE622N
I
u
CMOS
P10
N10
CKOP
CKON
O
LVDS
A5
FREQCKO
I
u
CMOS
B4
MUTECKON
I
u
CMOS
P12
N12
REFCLKP
REFCLKN
I
LVDS
A4
REFFREQ
I
u
CMOS
C2
RREFLVDS
I
Analog
D9
ACM
I
Analog
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