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參數(shù)資料
| 型號(hào)： | TRCV0110G |
| 廠商： | Lineage Power |
| 英文描述： | 10 Gbits/s Clock Recovery, 1:16 Data Multiplexer(10 G位/秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)多路復(fù)用器) |
| 中文描述： | 10 Gb /秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)復(fù)用器（10政位/秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)多路復(fù)用器） |
| 文件頁(yè)數(shù)： | 11/24頁(yè) |
| 文件大小： | 524K |
| 代理商： | TRCV0110G |
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Advance Data Sheet
August 2000
TRCV0110G
10 Gbits/s Clock Recovery, 1:16 Data Demultiplexer
11
Lucent Technologies Inc.
Functional Overview
The TRCV0110G performs the data detection, clock recovery, and 1:16 demultiplexing operations required to sup-
port 10 Gbits/s* OC-192/STM-64 applications compliant with Telcordia Technologiesand ITU standards. One of
two CML logic level inputs can be selected as the data source. A PLL recovers the clock which is used to retime
the data. A 1:16 data demultiplexer performs the serial-to-parallel conversion and generates 16 parallel outputs at
a 622 Mbits/s. The parallel output data is aligned to a 622 MHz clock derived from the 10 GHz recovered clock.
FEC Rate Support
The TRCV0110G will support both the normal OC-192/STM-64 rate of 9.9532 GHz and the forward error correc-
tion (FEC) rate of 10.6642 GHz. The FECN pin selects the rate the part is operating at. Throughout this document,
the specifications are given in terms of the normal operating rate only. All frequency-based specifications are to be
multiplied by 15/14 when operating at the FEC rate and all time-based specifications, with the exception of electri-
cal signal rise and fall times, are to be multiplied by 14/15 when operating at the FEC rate. For example, the refer-
ence clock would need to be applied at 166.628 MHz or 666.515 MHz and the parallel data interface would
operate at 666.515 MHz when FECN = 0.
Clock and Data Recovery (CDR)
Data Input Circuit
As shown in Figure 3 the DATAP/N inputs should be ac-coupled. These ac-coupling capacitors are typically
included inside the optical receiver package. For applications using discrete TIAs and small signal amplifiers, insert
low ESR 0.047
μ
F capacitors in the transmission line path. The 50
transmission lines are terminated with on-
chip 50
resistors. Great care must be taken in the design and layout of these critical transmission lines.
ACM pin should be connected with a low inductance, low ESR 0.047
μ
F capacitor to ground. This capacitor pro-
vides an RF bypass for common-mode noise that may be present on the data input pins. This capacitor should be
mounted as close as possible to the device package.
0364(F)r.1
Figure 3. Data Input Circuit
* The OC-192/STM-64 data rate of 9.95328 Gbits/s is typically approximated as 10 Gbits/s in this document when referring to the application
rate. Similarly, the low-speed parallel interface data rate of 622.08 Mbits/s is typically approximated as 622 Mbits/s. The exact frequencies are
used only when necessary for clarity.
50
50
BIAS
DATAP
DATAN
ACM
0.047
μ
F
0.047
μ
F
FROM
OPTICAL
RECEIVER
0.047
μ
F
DATA
INPUT
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