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參數(shù)資料
| 型號(hào)： | TRCV0110G |
| 廠商： | Lineage Power |
| 英文描述： | 10 Gbits/s Clock Recovery, 1:16 Data Multiplexer(10 G位/秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)多路復(fù)用器) |
| 中文描述： | 10 Gb /秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)復(fù)用器（10政位/秒時(shí)鐘恢復(fù)，1:16數(shù)據(jù)多路復(fù)用器） |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 524K |
| 代理商： | TRCV0110G |
Advance Data Sheet
August 2000
TRCV0110G
10 Gbits/s Clock Recovery, 1:16 Data Demultiplexer
7
Lucent Technologies Inc.
Pin Information
(continued)
Note:
In Table 2, when operating the TRCV0110G device at the OC-192/STM-64 rate, 10 Gbits/s should be
interpreted as 9.9532 Gbits/s. When operating the TRCV0110G device at the RS FEC OC-192/STM-64
rate, 10 Gbits/s should be interpreted as 10.6642 Gbits/s.
Table 2. Pin Descriptions—10 Gbits/s and Related Signals
* Differential pins are indicated by the P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
I = input, O = output. I
u
= an internal pull-up resistor on this pin, I
d
= an internal pull-down resistor on this pin, I
t
= an internal termination
resistance of 50
on this pin.
Pin
A9
A7
Symbol
*
DATAP
DATAN
Type
I
t
Level
CML
Name/Description
Data Input for 10 Gbits/s CML.
Primary data input.
Note that this data rate will scale by 15/14 when operating
at the FEC rate.
Loopback Data Input for 10 Gbits/s CML.
Use this input
for system loopback data. Note that this data rate will scale
by 15/14 when operating at the FEC rate.
FEC Rate (Active-Low).
Selects the normal OC-192/
STM-64 rate of 9.9532 GHz or the FEC rate of
10.6642 GHz.
D14
F14
LBDP
LBDN
I
t
CML
A3
FECN
I
u
CMOS
0 = FEC rate of 10.6642 GHz
1 or no connection = OC-192/STM-64 rate of 9.9532 GHz
Note that all input and output clock and data rates are
scaled by 15/14 when operating at the FEC rate.
Enable LBDP/N Inputs (Active-Low).
Selects LBDP/N as
data source rather than primary data input.
0 = select LBDP/N
1 or no connection = select DATAP/N
Resistor Reference VCO.
VCO bias reference resistor.
Connect a
TBD
k
resistor to V
CCD
.
Resistor Reference Charge Pump.
Charge pump bias
resistor. Connect a
TBD
k
resistor to V
CCD
.
Loss of Lock (Active-Low).
0 = PLL out of lock
Loop Filter PLL.
Connect LFP and LFN to loop filter (see
Figure 4, page 12).
C1
ENLBDN
I
u
CMOS
L14
RREFVCO
I
Analog
H14
RREFCP
I
Analog
B3
LCKLOSSN
O
CMOS
K14
J14
LFP
LFN
O
Analog
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