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參數(shù)資料
| 型號： | TRCV0110G |
| 廠商： | Lineage Power |
| 英文描述： | 10 Gbits/s Clock Recovery, 1:16 Data Multiplexer(10 G位/秒時鐘恢復，1:16數(shù)據(jù)多路復用器) |
| 中文描述： | 10 Gb /秒時鐘恢復，1:16數(shù)據(jù)復用器（10政位/秒時鐘恢復，1:16數(shù)據(jù)多路復用器） |
| 文件頁數(shù)： | 12/24頁 |
| 文件大小： | 524K |
| 代理商： | TRCV0110G |
TRCV0110G
10 Gbits/s Clock Recovery, 1:16 Data Demultiplexer
Advance Data Sheet
August 2000
12
Lucent Technologies Inc.
Clock and Data Recovery (CDR)
(continued)
Clock Recovery Operation
The CDR circuit uses a PLL to extract the clock and retime the 10 Gbits/s data. A 622 MHz clock derived from the
recovered clock is available as an output at CK622P/N. A 622 MHz or 155 MHz clock derived from the recovered
clock is available as an output at CKOP/N.
Clock Recovery PLL Loop Filter
A typical loop filter is shown in Figure 4. Connect the filter components and also connect LFP to VCP and connect
LFN to VCN. The component values can be varied to adjust the loop dynamic response (see Table 6).
Table 6. Clock Recovery Loop Filter Component Values
* Capacitor C1 should be either ceramic or nonpolar.
5-8061(F).b
Figure 4. Clock Recovery PLL Loop Filter Components
Components
C1*
C2, C3
R1
Values for 8 MHz Loop Bandwidth
TBD
μ
F ± 10%
TBD
pF ± 20%
TBD
± 5%
C
3
C
2
C
1
R
1
LFN/VCN
LFP/VCP
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