- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384023 > TMX320C6205ZHKA200 (Texas Instruments, Inc.) FIXED-POINT DIGITAL SIGNAL PROCESSOR PDF資料下載
參數(shù)資料
| 型號： | TMX320C6205ZHKA200 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 定點數(shù)字信號處理器 |
| 文件頁數(shù)： | 60/72頁 |
| 文件大?。?/td> | 1143K |
| 代理商： | TMX320C6205ZHKA200 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁當前第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
SPRS106G OCTOBER 1999 REVISED JULY 2006
60
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0
(see Figure 36)
200
NO.
MASTER
MIN
SLAVE
MIN
UNIT
MAX
MAX
4
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
12
2 3P
ns
5
Hold time, DR valid after CLKX high
4
5 + 6P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 0
(see Figure 36)
200
NO.
PARAMETER
MASTER§
SLAVE
UNIT
MIN
MAX
MIN
MAX
1
th(CKXL-FXL)
td(FXL-CKXH)
td(CKXL-DXV)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high#
L 2
L + 3
ns
2
T 2
T + 3
ns
3
Delay time, CLKX low to DX valid
2
4
3P + 4
5P + 17
ns
6
tdis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
CLKX low
2
4
3P + 3
5P + 17
ns
7
td(FXL-DXV)
Delay time, FSX low to DX valid
H 2
H + 4
2P + 2
4P + 17
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S =
sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T =
CLKX period = (1 + CLKGDV) * S
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
3
7
6
2
1
CLKX
FSX
DX
DR
5
Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
相關PDF資料 |
PDF描述 |
|---|---|
| TMP320C6205GHK200 | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6205GHKA200 | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6205ZHK200 | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6205ZHKA200 | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMX320DM6446ZWT | Digital Media System on-Chip |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMX320C6211BGDP167 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6211BGFN167 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6211BGGP100 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMX320C6211BGGP167 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMX320C6211BGHK100 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
發(fā)布緊急采購，3分鐘左右您將得到回復。