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參數(shù)資料
| 型號(hào)： | TMX320C6205ZHKA200 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 16/72頁(yè) |
| 文件大小： | 1143K |
| 代理商： | TMX320C6205ZHKA200 |
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SPRS106G OCTOBER 1999 REVISED JULY 2006
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Signal Descriptions (Continued)
SIGNAL
TYPE
DESCRIPTION
NAME
NO.
PCI INTERFACE (CONTINUED)
PINTA
C1
O/Z
PCI interrupt A
PREQ
F2
O/Z
PCI bus request (bus arbitration)
PSERR
P5
O/Z
PCI system error
PPERR
P2
I/O/Z
PCI parity error
PRST
C2
I
PCI reset
PDEVSEL
R2
I/O/Z
PCI device select
PGNT
D1
I
PCI bus grant (bus arbitration)
PFRAME
N5
I/O/Z
PCI frame
PIRDY
P1
I/O/Z
PCI initiator ready
PPAR
T3
I/O/Z
PCI parity
PIDSEL
H5
I
PCI initialization device select
PSTOP
R1
I/O/Z
PCI stop
PTRDY
N3
I/O/Z
PCI target ready
XSP_CLK
C17
O
Serial EEPROM clock
Serial EEPROM data in, pulldown with a dedicated 20-k
resistor
Serial EEPROM data out
XSP_DI
C18
I
XSP_DO
B19
O
XSP_CS
C11
O
Serial EEPROM chip select
3.3VauxDET
B1
I
3.3-V auxiliary power supply detect.
Used to indicate the presence of 3.3Vaux. A weak pulldown must be implemented to this pin.
3.3Vaux
B2
S
3.3-V auxiliary power supply voltage
PME
D3
O
Power management event
PWR_WKP
A2
I
Power wakeup signal
EMIF CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3
V18
Memory space enables
Enabled by bits 24 and 25 of the word address
Only one asserted during any external data access
CE2
U17
O/Z
CE1
W18
CE0
V17
BE3
U16
Byte-enable control
Decoded from the two lowest bits of the internal address
Can be directly connected to SDRAM read and write mask signal (SDQM)
BE2
W17
O/Z
BE1
V16
BE0
W16
Byte-write enables for most types of memory
EMIF ADDRESS
EA21
V7
EA20
W7
EA19
U8
O/Z
External address (word address)
EA18
EA17
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
V8
W8
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