參數(shù)資料
型號(hào): TMX320C6205ZHKA200
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSOR
中文描述: 定點(diǎn)數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 47/72頁(yè)
文件大?。?/td> 1143K
代理商: TMX320C6205ZHKA200
SPRS106G OCTOBER 1999 REVISED JULY 2006
47
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles
(see Figure 27)
NO.
200
UNIT
MIN
MAX
3
toh(HOLDAL-HOLDL)
Output hold time, HOLD low after HOLDA low
P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles
(see Figure 27)
NO.
PARAMETER
200
UNIT
MIN
MAX
1
td(HOLDL-EMHZ)
td(EMHZ-HOLDAL)
td(HOLDH-EMLZ)
td(EMLZ-HOLDAH)
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
§All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with
external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the
minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
Delay time, HOLD low to EMIF Bus high impedance
4P
§
ns
2
Delay time, EMIF Bus high impedance to HOLDA low
0
2P
ns
4
Delay time, HOLD high to EMIF Bus low impedance
3P
7P
ns
5
Delay time, EMIF Bus low impedance to HOLDA high
0
2P
ns
HOLD
HOLDA
EMIF Bus
DSP Owns Bus
External Requestor
Owns Bus
DSP Owns Bus
C6205
C6205
1
3
2
5
4
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
Figure 27. HOLD/HOLDA Timing
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