參數(shù)資料
型號： TMX320C6205ZHKA200
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSOR
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 38/72頁
文件大小： 1143K
代理商： TMX320C6205ZHKA200
SPRS106G OCTOBER 1999 REVISED JULY 2006
38
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles
§
(see Figure 15 Figure 18)
NO.
200
UNIT
MIN
MAX
3
tsu(EDV-AREH)
th(AREH-EDV)
tsu(ARDYH-AREL)
th(AREL-ARDYH)
tsu(ARDYL-AREL)
th(AREL-ARDYL)
tw(ARDYH)
tsu(ARDYH-AWEL)
th(AWEL-ARDYH)
tsu(ARDYL-AWEL)
th(AWEL-ARDYL)
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
§P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
Setup time, EDx valid before ARE high
1.5
ns
4
Hold time, EDx valid after ARE high
3.5
ns
6
Setup time, ARDY high before ARE low
[(RST 3) * P 6]
ns
7
Hold time, ARDY high after ARE low
(RST 3) * P + 3
ns
9
Setup time, ARDY low before ARE low
[(RST 3) * P 6]
ns
10
Hold time, ARDY low after ARE low
(RST 3) * P + 3
ns
11
Pulse width, ARDY high
2P
ns
15
Setup time, ARDY high before AWE low
[(WST 3) * P 6]
ns
16
Hold time, ARDY high after AWE low
(WST 3) * P + 3
ns
18
Setup time, ARDY low before AWE low
[(WST 3) * P 6]
ns
19
Hold time, ARDY low after AWE low
(WST 3) * P + 3
ns
switching characteristics over recommended operating conditions for asynchronous memory
cycles
§#
(see Figure 15 Figure 18)
NO.
PARAMETER
200
UNIT
MIN
TYP
MAX
1
tosu(SELV-AREL)
toh(AREH-SELIV)
tw(AREL)
td(ARDYH-AREH)
tosu(SELV-AWEL)
toh(AWEH-SELIV)
tw(AWEL)
td(ARDYH-AWEH)
Output setup time, select signals valid to ARE low
RS * P 2
ns
2
Output hold time, ARE high to select signals invalid
RH * P 2
ns
5
Pulse width, ARE low
RST * P
ns
8
Delay time, ARDY high to ARE high
3P
4P + 5
ns
12
Output setup time, select signals valid to AWE low
WS * P 2
ns
13
Output hold time, AWE high to select signals invalid
WH * P 2
ns
14
Pulse width, AWE low
WST * P
ns
17
Delay time, ARDY high to AWE high
3P
4P + 5
ns
RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
§P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
#Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional
7P ns following the end of the cycle.
相關(guān)PDF資料
PDF描述
TMP320C6205GHK200 FIXED-POINT DIGITAL SIGNAL PROCESSOR
TMP320C6205GHKA200 FIXED-POINT DIGITAL SIGNAL PROCESSOR
TMP320C6205ZHK200 FIXED-POINT DIGITAL SIGNAL PROCESSOR
TMP320C6205ZHKA200 FIXED-POINT DIGITAL SIGNAL PROCESSOR
TMX320DM6446ZWT Digital Media System on-Chip
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMX320C6211BGDP167 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMX320C6211BGFN167 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMX320C6211BGGP100 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR
TMX320C6211BGGP167 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS
TMX320C6211BGHK100 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*