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參數(shù)資料
| 型號： | TMS6644148 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 4 194 304 4位/ 2 097 152 8位/ 1 048 576由16位4，銀行同步動態(tài)隨機存取記憶體 |
| 文件頁數(shù)： | 22/56頁 |
| 文件大?。?/td> | 958K |
| 代理商： | TMS6644148 |
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TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
22
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
capacitance over recommended ranges of supply voltage and operating ambient temperature
f = 1 MHz (see Note 11)
PARAMETER
MIN
MAX
UNIT
Ci(S)
Ci(AC)
Ci(E)
Co
NOTE 11: VCC = 3.3
±
0.3 V and bias on pins under test is 0 V.
Input capacitance, CLK input
2.5
4
pF
Input capacitance, address and control inputs: A0–A13, CS, DQMx, RAS, CAS, W
2.5
5
pF
Input capacitance, CKE input
5
pF
Output capacitance
4
6.5
pF
ac timing requirements
’664xx4-8
MIN
’664xx4-8A
MIN
’664xx4-10
MIN
UNIT
MAX
MAX
MAX
tCK2
tCK3
tCH
tCL
Cycle time, CLK
CAS latency = 2
10
15
15
ns
Cycle time, CLK
CAS latency = 3
8
8
10
ns
Pulse duration, CLK high
3
3
3
ns
Pulse duration, CLK low
3
3
3
ns
tAC2
Access time, CLK high to data out
(see Note 12)
CAS latency = 2
6
7.5
7.5
ns
tAC3
Access time, CLK high to data out
(see Note 12)
CAS latency = 3
6
6
7.5
ns
tOH2
Hold time, CLK high to data out with 50-pF
load
CAS latency = 2
3
3
3
ns
tOH3
Hold time, CLK high to data out with 50-pF
load
CAS latency = 3
3
3
3
ns
tLZ
Delay time, CLK high to DQ in low-impedance state (see Note 13)
1
1
2
ns
tHZ
Delay time, CLK high to DQ in high-impedance state
(see Note 14)
8
8
10
ns
tIS
tIH
tCESP
tRAS
Setup time, address, control, and data input
2
2
2
ns
Hold time, address, control, and data input
1
1
1
ns
Power down/self-refresh exit time (see Note 15)
8
8
10
ns
Delay time, ACTV command to DEAC or DCAB command
48
100000
48
100000
50
100000
ns
tRC
Delay time, ACTV, REFR, or SLFR command to ACTV, MRS,
REFR, or SLFR command
68
68
80
ns
tRCD
Delay time, ACTV command to READ, READ-P, WRT, or
WRT-P command (see Note 16)
20
20
30
ns
tRP
Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or
SLFR command
20
20
30
ns
tRRD
Delay time, ACTV command in one bank to ACTV command in
the other bank
16
16
20
ns
tRSA
Delay time, MRS command to ACTV, MRS, REFR, or SLFR
command
See Parameter Measurement Information for load circuits (see Figure 9).
All references are made to the rising transition of CLK, unless otherwise noted.
NOTES: 12. tAC is referenced from the rising transition of CLK that precedes the data-out cycle. For example, the first data-out tAC is referenced
from the rising transition of CLK that is CAS latency – one cycle after the READ command. An access time is measured at output
reference level 1.5 V.
13. tLZ is measured from the rising transition of CLK that is CAS latency – one cycle after the READ command.
14. tHZ MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.
15. See Figure 18 and Figure 19.
16. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.
16
16
20
ns
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMS6644148A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS664414DGE-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X4MX4|CMOS|TSOP|54PIN|PLASTIC |
| TMS664414DGE-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X4MX4|CMOS|TSOP|54PIN|PLASTIC |
| TMS664414DGE-8A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X4MX4|CMOS|TSOP|54PIN|PLASTIC |
| TMS664814 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
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