參數(shù)資料
型號(hào): TMS6644148
廠商: Texas Instruments, Inc.
英文描述: 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
中文描述: 4 194 304 4位/ 2 097 152 8位/ 1 048 576由16位4,銀行同步動(dòng)態(tài)隨機(jī)存取記憶體
文件頁數(shù): 15/56頁
文件大?。?/td> 958K
代理商: TMS6644148
TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
15
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupted bursts (continued)
nCCD = 2
CLK
DQ
READ Command
at Column Address C0
(see Note A)
C0
C0 + 1
C1
C1 + 1
C1 + 2
First Output Cycle for New
READ Command Begins Here
Interrupting
READ Command
at Column Address C1
(see Note A)
a) INTERRUPTED ON EVEN CYCLES
nCCD = 3
CLK
DQ
READ Command
at Column Address C0
(see Note A)
C0
C0 + 1
C0 + 2
C1
C1 + 1
First Output Cycle for New
READ Command Begins Here
Interrupting
READ Command
at Column Address C1
(see Note A)
b) INTERRUPTED ON ODD CYCLES
NOTE A: For this example, assume CAS latency = 2 and burst length > 2.
Figure 3. Read Burst Interrupted by Read Command
nCCD = 4
CLK
DQ
READ Command
at Column Address C0
(see Note A)
Interrupting
WRT Command
at Column Address C1
(see Note A)
C0
C1
C1 + 1
C1 + 2
First Input Cycle for New WRT
Command Begins Here
DQMx
See Note B
nCCD – 1
nCCD + 1
NOTES: A. For this example, read latency = 2 and burst length > 2.
B. DQMx must be high to mask output of the read burst on cycles (nCCD–1), (nCCD), and (nCCD+1).
Figure 4. Read Burst Interrupted by Write Command
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