參數(shù)資料
型號： TMS320LC17
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(278ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
中文描述： 數(shù)字信號處理器（278ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的數(shù)字信號處理器）
文件頁數(shù)： 81/139頁
文件大?。?/td> 1478K
代理商： TMS320LC17
I/O/Z
DESCRIPTION
I/O/Z
TMS320C16
DIGITAL SIGNAL PROCESSOR
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
81
TERMINAL FUNCTIONS (concluded)
PIN
DESCRIPTION
NAME
NO.
INTERRUPT AND MISCELLANEOUS SIGNALS
External polling input. Polled by BIOZ instruction. If low, the device branches to the address
specified by the instruction.
BIO
64
I
IOEN
54
O
Data enable for device input data. When active (low), IOEN indicates that the device will
accept data from the data bus. IOEN is active only during the IN instruction. When IOEN is
active, MEN, IOWE, and MWE will always be inactive (high).
IOWE
52
O
Write enable for device output data. When active (low), IOWE indicates that data will be
output from the device on the data bus. IOWE is active only during the OUT instruction. When
IOWE is active, MEN, IOEN, and MWE will always be inactive (high).
INT
63
I
External interrupt input. The interrupt signal is generated by applying a negative-going edge
to the INT pin. The edge is used to latch the interrupt flag register (INTF) until an interrupt
is granted by the device. An active low level will also be sensed.
MC/MP
62
I
Memory mode select pin. High selects the microcomputer mode, in which 8K words of
on-chip program memory are available. A low on MC/MP pin enables the microprocessor
mode. In this mode, the entire memory space is external; i.e., addresses 0 through 65535.
MEN
56
O
Memory enable. MEN is an active (low) control signal generated by the device to enable
instruction fetches from program memory. MEN will be active on instructions fetched from
both internal and external memory. When MEN is active, MWE, IOWE, and IOEN will be
inactive (high).
MWE
53
O
Write enable for device output data. When active (low), MWE indicates that data will be
output from the device on the data bus. MWE is active only during the TBLW instruction.
When MWE is active, MEN, IOEN, and IOWE will always be inactive (high).
NC
1, 12, 18, 19,
24, 29, 33,
50, 51, 55
—
No connection.
RS
2
I
Schmitt-triggered input for initializing the device. When held active for a minimum of five
clock cycles. IOEN, IOWE, MWE, and MEN are forced high; and, the data bus (D15 through
D0) is not driven. The program counter (PC) and the address bus (A15 through A0) are then
synchronously cleared after the next complete clock cycle from the falling edge of RS. Reset
also disables the interrupt, clears the interrupt flag register, and leaves the overflow mode
register unchanged. The device can be held in the reset state indefinitely.
SUPPLY/OSCILLATOR SIGNALS
PIN
NAME
NO.
CLKOUT
9
O
System clock output (one-fourth crystal/CLKIN frequency).
VDD
26, 57, 58,
59, 60
I
5-V suppy pins.
VSS
5, 6, 7, 8,
42, 61
I
Ground pins.
X1
3
O
Crystal output pin for internal oscillator. If the internal oscillator is not used, this pin should
be left unconnected.
X2/CLKIN
4
I
Input pin to the internal oscillator (X2) from the crystal. Alternatively, an input pin for an
external oscillator (CLKIN).
Input/Output/High-impedance state.
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