參數(shù)資料
型號： TMS320LC17
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors(278ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的DSP)
中文描述： 數(shù)字信號處理器（278ns指令周期，分離的程序和數(shù)據(jù)總線，外部輪詢中斷的數(shù)字信號處理器）
文件頁數(shù)： 67/139頁
文件大?。?/td> 1478K
代理商： TMS320LC17
TMS320E15, TMS320P15
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
67
Table 5 shows the programming levels required for programming, verifying, reading, and protecting the EPROM cell.
Table 5. TMS320E15/P15 Programming Mode Levels
SIGNAL NAME
TMS320E15 PIN
TMS27C64 PIN
PROGRAM
VERIFY
READ
PROTECT VERIFY
EPROM PROTECT
E
25
20
VIL
VIH
PULSE
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VPP
VCC + 1
VSS
VSS
VSS
VPP
Q8=PULSE
G
24
22
PULSE
PULSE
PGM
23
27
VIH
VPP
VCC
VSS
VSS
VSS
VSS
QOUT
ADDR
VIH
VCC
VCC
VSS
VSS
VSS
VSS
QOUT
ADDR
VPP
VCC
VSS
CLKIN
3
1
VPP
VCC
VSS
VSS
VSS
VSS
DIN
ADDR
VCC + 1
VCC + 1
VSS
VSS
VSS
VPP
Q8=RBIT
30
28
10
14
8
14
RS
4
14
EPT
5
26
Q1-Q8
11-18
11-13, 15-19
A0-A3
2, 1, 40, 39
10-7
X
X
A4
38
6
ADDR
ADDR
ADDR
X
VIH
X
A5
37
5
ADDR
ADDR
ADDR
X
A6
36
4
ADDR
ADDR
ADDR
VIL
X
X
A7-A9
35, 34, 29
3, 25, 24
ADDR
ADDR
ADDR
X
A10-A12
28-26
21, 23, 2
ADDR
ADDR
ADDR
X
X
Legend:
VIH = TTL high level; VIL = TTL low level; ADDR = byte address bit
VPP = 12.5 V
±
0.25 V; VCC = 5 V
±
0.25 V; X = don’t care
PULSE = low-going TTL level pulse; DIN = byte to be programmed at ADDR
QOUT = byte stored at ADDR; RBIT = ROM protect bit.
programming
Since every memory bit in the cell is a logic 1, the programming operation reprograms certain bits to 0. Once
programmed, these bits can only be erased using ultraviolet light. The correct byte is placed on the data bus
with V
PP
set to the 12.5 V level. The PGM pin is then pulsed low to program in the zeros.
erasure
Before programming, the device must be erased by exposing it to ultraviolet light. The recommended minimum
exposure dose (UV-intensity
×
exposure-time) is 15 W
s/cm
2
. A typical 12-mW/cm
2
, filterless UV lamp will erase
the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After
exposure, all bits are in the high state.
verify/read
To verify correct programming, the EPROM cell can be read using either the verify or read line definitions shown
in Table 5, assuming the inhibit bit has not been programmed.
program inhibit
Programming may be inhibited by maintaining a high level input on the E pin or PGM pin.
read
The EPROM contents may be read independent of the programming cycle, provided the RBIT (ROM protect
bit) has not been programmed. The read is accomplished by setting E to zero and pulsing G low. The contents
of the EPROM location selected by the value on the address inputs appear on Q8-Q1.
相關PDF資料
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