參數(shù)資料
型號(hào): TMS320LC17
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processors(278ns指令周期,分離的程序和數(shù)據(jù)總線,外部輪詢中斷的DSP)
中文描述: 數(shù)字信號(hào)處理器(278ns指令周期,分離的程序和數(shù)據(jù)總線,外部輪詢中斷的數(shù)字信號(hào)處理器)
文件頁數(shù): 39/139頁
文件大?。?/td> 1478K
代理商: TMS320LC17
RL = 825
,
CL = 100 pF,
(see Figure 2)
RL = 825
,
CL = 100 pF,
(see Figure 2)
RL = 825
,
CL = 100 pF,
(see Figure 2)
TMS320C14, TMS320E14, TMS320P14
DIGITAL SIGNAL PROCESSORS
SPRS009C–JANUARY 1987–REVISED JULY 1991
POST OFFICE BOX 1443
HOUSTON, TEXAS 77001
39
MICROCOMPUTER/MICROPROCESSOR MODE (NMI/MC/MP)
timing requirements over recommended operating conditions
MIN
NOM
MAX
UNIT
th(MC/MP)
Values were derived from characterization data and not tested.
Hold time to put device in microprocessor mode.
Hold time after RS high
tc(C)
ns
INTERRUPT (INT)/NONMASKABLE INTERRUPT (NMI)
timing requirements over recommended operating conditions
MIN
NOM
MAX
15
15
UNIT
tf(INT)
tf(NMI)
tw(INT)
tw(NMI)
tsu(INT)
tsu(NMI)
Fall time, INT
ns
Fall time, NMI
ns
Pulse duration, INT
tc(C)
tc(C)
60
ns
Pulse duration, NMI
ns
Setup time, INT before CLKOUT low (see Note 12)
ns
Setup time, NMI before CLKOUT low (see Note 12)
60
ns
NOTE 12: INT and NMI are synchronous inputs and can occur at any time during the cycle. NMI and INT are edge triggered only.
BIT I/O TIMING
switching characteristics over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
20
UNIT
trfo(IOP)
td(IOP)
Rise and fall time outputs
ns
CLKOUT low to data valid outputs
0.75 tc(C)+80
ns
timing requirements over recommended operating conditions
TEST CONDITIONS
MIN
NOM
MAX
20
UNIT
ns
trfl(IOP)
tsu(IOP)
tw(IOP)
Rise and fall time inputs
Data setup time before CLKOUT time
40
ns
Input pulse duration
tc(C)
ns
GENERAL PURPOSE TIMERS
timing requirements over recommended operating conditions
TEST CONDITIONS
MIN
NOM
MAX
20
20
UNIT
tr(TIM)
tf(TIM)
twl(TIM)
twh(TIM)
tclk(TIM)
Values were derived from characterization data and not tested.
TCLK1, TCLK2 rise time
ns
TCLK1, TCLK2 fall time
ns
TCLK1, TCLK2 low time
tc(C)+20
tc(C)+20
2 c(C)+40
ns
TCLK1, TCLK2 high time
ns
Input pulse duration
ns
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