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參數(shù)資料
| 型號： | TMS320AV120 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MPEG Audio Decoder(MPEG音頻譯碼器) |
| 中文描述： | MPEG音頻解碼器（的MPEG音頻譯碼器） |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 380K |
| 代理商： | TMS320AV120 |
TMS320AV120
MPEG AUDIO DECODER
SCSS014A – MARCH 1994 – REVISED JANUARY 1996
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PCM output interface (continued)
The decoder requires a clock input (PCMCLK) that is at the proper multiple of the sampling frequency. The
sampling frequency of the MPEG stream being decoded is indicated by the SF1:0 bits in the status register. The
PCMCLK input frequency depends on the sampling frequency and oversampling ratio as shown in Table 3. PCM
output timing is shown in Figure 6.
Table 3. PCMCLK Frequency Selection Summary
ááááááááááááááááááááááá
ááááááááááááááááááááá
á
áááááááááááááááááááááá
ááááááááááááááááááááá
ááááááááááááááááááááá
ááááááááááááááááááááááá
FREQUENCY
PCMSEL1:0 (00)
PCMSEL1:0 (01)
PCMSEL1:0 (10)
PCMSEL1:0 (11)
32
á
1.024
áááá
32 x LRCLK
(MHz)
á
8.192
PCMCLK =
256 x LRCLK
(MHz)
á
1.536
PCMCLK =
8 x SCLK =
áááá
48 x LRCLK
(MHz)
á
12.288
PCMCLK =
áááá
384 x LRCLK
(MHz)
á
PCMCLK =
ááááááááááááááááááááá
td1
td1
td2
td3
td3
td4
Left Bit 15
Left Bit 14
Left Bit 0
Right Bit 15
Right Bit 14
SCLK
LRCLK
PCMOUT
BOF
PCMSEL1
First bit of frame as indicated by BOF
Figure 6. PCM Output Timing
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