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參數(shù)資料
| 型號(hào)： | TMS320AV120 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MPEG Audio Decoder(MPEG音頻譯碼器) |
| 中文描述： | MPEG音頻解碼器（的MPEG音頻譯碼器） |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大?。?/td> | 380K |
| 代理商： | TMS320AV120 |
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TMS320AV120
MPEG AUDIO DECODER
SCSS014A – MARCH 1994 – REVISED JANUARY 1996
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PCMCLK error signal
In order to facilitate synchronization of the PCMCLK frequency to the input-data rate, the TMS320AV120
generates an error signal that is proportional to the average difference between the ICLK and the PCMCLK
frequencies. The error signal is a pulse-width-modulated pulse train at a frequency equal to twice the sampling
frequency. A 50% duty cycle indicates no error (see Figure 9). A VXO control voltage is derived from the PWM
signal by low-pass filtering and any required level shifting. Duty-cycle adjustments are
±
0.2%,
with an
integration time of approximately 2 seconds giving a very stable, low-loop-gain system.
PCM_ERR is only valid when the compressed-data input is at the bit rate of the compressed data. In general,
SREQ must be low at all times for the error signal to be valid. This is the exact opposite of the input-data rate
required for audio/video synchronization; the two modes can not be used at the same time.
td7
td8
td8
PCM_ERR
td7
td8
td8
PCM_ERR
td7
td8
td8
PCM_ERR
(a) PCMCLK and ICLK Synchronized
(b) PCMCLK Slow
(c) PCMCLK Fast
Figure 9. PCM_ERR-Output Timing
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相關(guān)代理商/技術(shù)參數(shù) |
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| TMS320AV120FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Audio Decoder & Support |
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| TMS320AV410PJM | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TMS320AV411 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Encoder Circuit |
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