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參數資料
| 型號： | TMS320AV120 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MPEG Audio Decoder(MPEG音頻譯碼器) |
| 中文描述： | MPEG音頻解碼器（的MPEG音頻譯碼器） |
| 文件頁數： | 7/17頁 |
| 文件大小： | 380K |
| 代理商： | TMS320AV120 |
TMS320AV120
MPEG AUDIO DECODER
SCSS014A – MARCH 1994 – REVISED JANUARY 1996
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
input interface (continued)
1/fclock
tsu1
tpd1
tsu3
th2
tsu3
th2
tsu4
th3
tw1
Data
SCR/PTS
Bit 0
SCR/PTS
Bit 33
Data
Data
ICLK
SREQ
SIN
SMODE
Figure 3. Burst-Data Input Timing
tsu5
th4
tw2
1st Bit
of Header
ICLK
HSYNC
SIN
Figure 4. HSYNC Input Timing
reset sequence
The ’AV120 must be reset during power up. Reset of the device is initiated by pulling RESET low. The following
actions occur:
– SREQ goes high.
– Serial input data is ignored.
– All data buffers (including the input buffer) are cleared.
– The PCM output is forced to mute.
When the reset sequence is finished (after multiple clock cycles), SREQ again goes low signaling that the device
is ready to accept compressed-data input. The first high-to-low transition on BOF signals the availability of valid
decoded audio data. A change in the bit rate, sampling frequency, or layer of the encoded bit stream requires
a reset. If a change in one of these parameters is detected without a reset, the ’AV120 forces a reset. Figure 5
shows reset timing.
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