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參數(shù)資料
| 型號： | TMS320AV120 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MPEG Audio Decoder(MPEG音頻譯碼器) |
| 中文描述： | MPEG音頻解碼器（的MPEG音頻譯碼器） |
| 文件頁數(shù)： | 10/17頁 |
| 文件大小： | 380K |
| 代理商： | TMS320AV120 |
TMS320AV120
MPEG AUDIO DECODER
SCSS014A – MARCH 1994 – REVISED JANUARY 1996
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ancillary-data-output interface
Ancillary data from each frame is output serially on ANCOUT. The rising edge of ANCCLK signals new valid data
is available on ANCOUT and can be used to latch it. When ANCCLK is switching, its frequency is equal to
one-half of the system clock at the XTAL1 input. If ancillary data is not needed for a specific application, these
terminals can be ignored. Figure 7 shows ancillary-data-output timing.
ANCCLK
ANCOUT
td5
2/(fclock XTAL1)
Figure 7. Ancillary-Data-Output Timing
status-register-output interface
The status register contains information from the header of each frame and on the status of the device. The
register can be read serially on STATOUT starting with the most significant bit (see Figure 8). Data is valid on
the rising edge of STATCLK. When STATCLK is switching, its frequency is equal to SCLK. The status register
is updated on the high-to-low transition of BOF. Table 4 shows the status-register-output order. Stereo mode,
sampling frequency, and de-emphasis information is output at the begining of the status-register stream for
convenience in addition to the MPEG header. The status register is not output in audio-bypass mode,
BYPASS = 1.
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