- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄199412 > TMP86CH09NG 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP32 PDF資料下載
參數(shù)資料
| 型號(hào)： | TMP86CH09NG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | 0.400 INCH, 1.78 MM PITCH, LEAD FREE, PLASTIC, SDIP-32 |
| 文件頁(yè)數(shù)： | 61/120頁(yè) |
| 文件大小： | 1743K |
| 代理商： | TMP86CH09NG |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)當(dāng)前第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)
Page 34
3. Interrupt Control Circuit
3.2 Interrupt enable register (EIR)
TMP86FH09ANG
Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to
"0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL
(Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on
interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL
should be executed before setting IMF="1".
3.2 Interrupt enable register (EIR)
The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable
interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Non-
maskable interrupt is accepted regardless of the contents of the EIR.
The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These
registers are located on address 003AH and 003BH in SFR area, and they can be read and written by an instructions
(Including read-modify-write instructions such as bit manipulation or operation instructions).
3.2.1 Interrupt master enable flag (IMF)
The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt.
While IMF = “0”, all maskable interrupts are not accepted regardless of the status on each individual interrupt
enable flag (EF). By setting IMF to “1”, the interrupt becomes acceptable if the individuals are enabled. When
an interrupt is accepted, IMF is cleared to “0” after the latest status on IMF is stacked. Thus the maskable inter-
rupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data,
which was the status before interrupt acceptance, is loaded on IMF again.
The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction.
The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initial-
ized to “0”.
3.2.2 Individual interrupt enable flags (EF15 to EF4)
Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding
bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting the bit to “0” dis-
ables acceptance. During reset, all the individual interrupt enable flags (EF15 to EF4) are initialized to “0” and
all maskable interrupts are not accepted until they are set to “1”.
Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear
IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF
or IL (Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute nor-
mally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulat-
ing EF or IL should be executed before setting IMF="1".
Example 1 :Clears interrupt latches
DI
; IMF
← 0
LDW
(ILL), 1110100000111111B
; IL12, IL10 to IL6
← 0
EI
; IMF
← 1
Example 2 :Reads interrupt latchess
LD
WA, (ILL)
; W
← ILH, A ← ILL
Example 3 :Tests interrupt latches
TEST
(ILL). 7
; if IL7 = 1 then jump
JR
F, SSET
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMP86CM29BU | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP64 |
| TMP86FH09NG | 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PDIP32 |
| TMP86FS49BUG | 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP64 |
| TMP86PS25F | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| TMP87C800N | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMP86CH12MG | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:8 Bit Microcontroller |
| TMP86CH21AUG | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:8 Bit Microcontroller |
| TMP86CH21F | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:CMOS 8-Bit Microcontroller |
| TMP86CH21U | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:CMOS 8-Bit Microcontroller |
| TMP86CH22UG | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:8 Bit Microcontroller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。