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參數(shù)資料
| 型號： | TMC22091KHC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Digital Video Encoders/Layering Engine |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP100 |
| 封裝： | 3.20 MM HEIGHT, MQFP-100 |
| 文件頁數(shù)： | 38/60頁 |
| 文件大?。?/td> | 293K |
| 代理商： | TMC22091KHC |
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TMC22091/TMC22191
PRODUCT SPECIFICATION
38
Genlocked Mode
In Genlocked mode, the encoder receives sync signals over
the GHSYNC and GVSYNC inputs, and provides VHSYNC
and VVSYNC to the host. The 50% sync amplitude point
occurs 50 PXCK clocks after GHSYNC goes LOW, while
VHSYNC is produced at clock 13. If GHSYNC is late, the
front porch is lengthened, if is is early, front porch is
shortened. See Figure 16, Genlock Mode Timing.
Pixel Data Control
The Pixel Data Control (PDC) signal determines the active
picture area. It may be an input or an output, as determined
by the Interface Control Register bit 1.
The position (number of PCK cycles) of the rising edge of
PDC relative to the falling edge of VHSYNC can be found
by summing SY, BU, BR, and CBP. See Figure 17.
External Pixel Data Control
When used as an input, PDC goes HIGH four PXCK cycles
before the first valid pixel of a line is presented to the PD
input port. If this signal is late (with respect to the horizontal
blanking interval programmed in the timing control regis-
ters), the Color Back Porch (CBP) will be extended. If it is
early, incoming pixel data will be ignored until the end of the
CBP.
Figure 15. Slave Mode Timing
Figure 16. Genlocked Mode Timing
PXCK
50% Sync Amplitude
24355A
COMPOSITE
OUTPUT
VHSYNC1
VVSYNC1
for field 1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PXCK
50% Sync Amplitude
24356A
COMPOSITE
OUTPUT
GHSYNC
VHSYNC
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMC22191KHC | Digital Video Encoders/Layering Engine |
| TMC22091R0C | Digital Video Encoders/Layering Engine |
| TMC22191R0C | Digital Video Encoders/Layering Engine |
| TMC22091 | Digital Video Encoders(數(shù)字視頻編碼器) |
| TMC22191 | Digital Video Encoders(數(shù)字視頻編碼器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC22091R0C | 功能描述:視頻 IC D/V Encoder Layering Engine RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TMC22091R0CT | 功能描述:視頻 IC D/V Encoder Layering Engine RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TMC22091ROC-T | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC22151AKHC | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
| TMC22151KHC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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