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參數(shù)資料
| 型號： | TLV320AIC3106IGQE |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY |
| 中文描述： | 低功耗立體聲音頻編解碼器的便攜式音頻/電話 |
| 文件頁數(shù)： | 30/102頁 |
| 文件大小： | 1259K |
| 代理商： | TLV320AIC3106IGQE |
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STEREO AUDIO ADC HIGH PASS FILTER
H(z)
N0
N1
z
1
32768
D1
z
1
(1)
DIGITAL AUDIO PROCESSING FOR RECORD PATH
In applications where record
only
is selected, and DAC is powered down, the playback path signal processing
blocks can be used in the ADC record path. These filtering blocks can support high pass, low pass, band pass
or notch filtering. In this mode, the record only path has switches SW-D1 through SW-D4 closed, and reroutes
the ADC output data through the digital signal processing blocks. Since the DAC's Digital Signal Processing
blocks are being re-used, naturally the addresses of these digital filter coefficients are the same as for the DAC
digital processing and are located on Page 1, Registers 1-52. This record only mode is enabled by powering
down both DACs by writing to Page 0, Register 37, bits D7-D6 (D7=D6=”0”). Next, enable the digital filter
pathway for the ADC by writing a “1” to Page 0, Register 107, bit D3. (Note, this pathway is only enabled if
both
DACs are powered down.) This record only path can be seen in
Figure 26
.
Audio Serial Bus Interface
PGA
0/+59.5dB
0.5dB steps
ADC
+
DAC
L
Volume
Control
D
D
B
W
D
D
D
D
ADC
PGA
0/+59.5dB
0.5dB steps
+
DACR
Volume
Control
Effects
AGC
AGC
Record Path
Record Path
DAC
Powered
Down
DAC
Powered
Down
Effects
SW-D1
SW-D2
SW-D3
SW-D4
Left Channel
Analog Inputs
Right Channel
Analog Inputs
TLV320AIC3106
SLAS509B–DECEMBER 2006–REVISED JUNE 2007
Often in audio applications it is desirable to remove the DC offset from the converted audio data stream. The
TLV320AIC3106 has a programmable first order high pass filter which can be used for this purpose. The Digital
filter coefficients are in 16-bit format and therefore use two 8-bit registers for each of the three coefficients of N0,
N1, and D1. The transfer function of the digital high pass filter is of the form:
Programming the Left channel is done by writing to Page 1, Registers 65-70, and the right channel is
programmed by writing to Page 1, Registers 71-76. After the coefficients have been loaded, these ADC high
pass filter coefficients can be selected by writing to Page 0, Register 107, D7-D6, and the high pass filter can be
enabled by writing to Page 0, Register 12, bits D7-D4.
Figure 26. Record
Only
Mode With Digital Processing Path Enabled
30
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV320AIC3106IGQER | 制造商:Texas Instruments 功能描述:AUD CODEC 2ADC / 2DAC 24BIT 80BGA - Tape and Reel |
| TLV320AIC3106IRGZR | 功能描述:接口—CODEC Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC3106IRGZT | 功能描述:接口—CODEC Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC3106IZQE | 功能描述:接口—CODEC Low-Power Stereo RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC3106IZQER | 功能描述:接口—CODEC Low-Power Stereo RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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