參數(shù)資料
型號(hào)： TLV320AIC3106IGQE
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
中文描述： 低功耗立體聲音頻編解碼器的便攜式音頻/電話
文件頁(yè)數(shù)： 27/102頁(yè)
文件大?。?/td> 1259K
代理商： TLV320AIC3106IGQE
www.ti.com
K*R/P
2/Q
GPIO2
PLL_CLKIN
CODEC
CODEC_CLKIN
PLL_OUT
K = J.D
J = 1,2,3,…..,62,63
D= 0000,0001,….,9998,9999
R= 1,2,3,4,….,15,16
P= 1,2,….,7,8
Q=2,3,…..,16,17
MCLK
BCLK
CLKDIV_IN
PLL_IN
WCLK = Fsref/ Ndac
GPIO1 = Fsref/ Nadc
ADC_FS
DAC_FS
Ndac=1,1.5,2,…..,5.5,6
DAC DRA => Ndac = 0.5
Nadc=1,1.5,2,…..,5.5,6
ADC DRA => Nadc = 0.5
CODEC_CLK=256*Fsref
CLKDIV_OUT
1/8
PLLDIV_OUT
CLKDIV_CLKIN
2/(N*M)
CLKMUX _OUT
GPIO1
M =1,2,4,8
N = 2,3,……,16,17
CLKOUT
CLKOUT_IN
TLV320AIC3106
SLAS509B–DECEMBER 2006–REVISED JUNE 2007
Figure 25. Audio Clock Generation Processing
The part can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a
programmable divider or a PLL, to get the proper internal audio master clock needed by the part. The BCLK or
GPIO2 inputs can also be used to generate the internal audio master clock.
This design also allows the PLL to be used for an entirely separate purpose in a system, if the audio codec is
not powered up. The user can supply a separate clock to GPIO2, route this through the PLL, with the resulting
output clock driven out GPIO1, for use by other devices in the system
A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies
available in the system. This device includes a highly programmable PLL to accommodate such situations
easily. The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with
particular focus paid to the standard MCLK rates already widely used.
When the PLL is disabled,
Fsref = CLKDIV_IN / (128
×
Q)
Where Q = 2, 3,
…
, 17
CLKDIV_IN can be MCLK, BCLK, or GPIO2, selected by register 102, bits D7-D6.
NOTE – when NDAC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode, MCLK can be as
high as 50 MHz, and Fsref should fall within 39 kHz to 53 kHz.
When the PLL is enabled,
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLV320AIC3106IGQER 制造商:Texas Instruments 功能描述:AUD CODEC 2ADC / 2DAC 24BIT 80BGA - Tape and Reel
TLV320AIC3106IRGZR 功能描述:接口—CODEC Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC3106IRGZT 功能描述:接口—CODEC Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC3106IZQE 功能描述:接口—CODEC Low-Power Stereo RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC3106IZQER 功能描述:接口—CODEC Low-Power Stereo RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
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