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參數(shù)資料
| 型號： | TLV320AIC3106IGQE |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY |
| 中文描述： | 低功耗立體聲音頻編解碼器的便攜式音頻/電話 |
| 文件頁數(shù)： | 23/102頁 |
| 文件大?。?/td> | 1259K |
| 代理商： | TLV320AIC3106IGQE |
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www.ti.com
Possible Processor Types:
Application Processor, Multimedia Processor,
Compressed Audio Decoder, Wireless Modem,
Bluetooth Module, Additional Audio/Voice Codec
Processor
2
Processor
1
G
W
B
D
D
M
G
AIC3106
RIGHT JUSTIFIED MODE
In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling
edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding
the rising edge of the word clock.
TLV320AIC3106
SLAS509B–DECEMBER 2006–REVISED JUNE 2007
Figure 19. AIC3106 Connected to Multiple Audio Devices
The audio bus of the TLV320AIC3106 can be configured for left or right justified, I
2
S, DSP, or TDM modes of
operation, where communication with standard telephony PCM interfaces is supported within the TDM mode.
These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word
clock (WCLK or GPIO1) and bit clock (BCLK or GPIO2) can be independently configured in either Master or
Slave mode, for flexible connectivity to a wide variety of processors
The word clock (WCLK or GPIO1) is used to define the beginning of a frame, and may be programmed as either
a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC
and DAC sampling frequencies.
The bit clock (BCLK or GPIO2) is used to clock in and out the digital audio data across the serial bus. When in
Master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock
mode. In continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are
generated, so in general the number of bit clocks per frame will be two times the data width. For example, if data
width is chosen as 16-bits, then 32 bit clocks will be generated per frame. If the bit clock signal in master mode
will be used by a PLL in another device, it is recommended that the 16-bit or 32-bit data width selections be
used. These cases result in a low jitter bit clock signal being generated, having frequencies of 32
×
Fs or 64
×
Fs.
In the cases of 20-bit and 24-bt data width in master mode, the bit clocks generated in each frame will not all be
of equal period, due to the device not having a clean 40
×
Fs or 48
×
Fs clock signal readily available. The average
frequency of the bit clock signal is still accurate in these cases (being 40
×
Fs or 48
×
Fs), but the resulting clock
signal has higher jitter than in the 16-bit and 32-bit cases.
In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen.
The TLV320AIC3106 further includes programmability to 3-state the DOUT line during all bit clocks when valid
data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the
audio data will begin, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to
use a single audio serial data bus.
When the audio serial data bus is powered down while configured in master mode, the pins associated with the
interface will be put into a 3-state output condition.
23
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLV320AIC3106IGQER | 制造商:Texas Instruments 功能描述:AUD CODEC 2ADC / 2DAC 24BIT 80BGA - Tape and Reel |
| TLV320AIC3106IRGZR | 功能描述:接口—CODEC Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC3106IRGZT | 功能描述:接口—CODEC Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC3106IZQE | 功能描述:接口—CODEC Low-Power Stereo RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC3106IZQER | 功能描述:接口—CODEC Low-Power Stereo RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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