參數(shù)資料
型號(hào)： TLV320AIC3106IGQE
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
中文描述： 低功耗立體聲音頻編解碼器的便攜式音頻/電話
文件頁(yè)數(shù)： 20/102頁(yè)
文件大?。?/td> 1259K
代理商： TLV320AIC3106IGQE
www.ti.com
CONTINUOUS READ / WRITE OPERATION
I
2
C CONTROL MODE
The TLV320AIC3106 supports the I
2
C control protocol when the SELECT pin is tied low, using 7-bit addressing
and capable of both standard and fast modes. When in I
2
C control mode, the TLV320AIC3106 can be
configured for one of four different addresses, using the multifunction pins MFP0 and MFP1, which control the
two LSBs of the device address. The 5 MSBs of the device address are fixed as 00110 and cannot be changed,
while the two LSBs are given by MFP1:MFP0. This results in four possible device addresses:
TLV320AIC3106
SLAS509B–DECEMBER 2006–REVISED JUNE 2007
addresses 1 to 127 will access registers in page 0. If registers on page 1 must be accessed, the user must write
the 8-bit sequence 0x01 to register 0, the page control register, to change the active page from page 0 to page
1. After this write, it is recommended the user also read back the page control register, to safely ensure the
change in page control has occurred properly. Future read/write operations to addresses 1 to 127 will now
access registers in page 1. When page 0 registers must be accessed again, the user writes the 8-bit sequence
0x00 to register 0, the page control register, to change the active page back to page 0. After a recommended
read of the page control register, all further read/write operations to addresses 1 to 127 will now access page 0
registers again.
Limitation on Register Writing
When writing registers in SPI mode related to the audio output drivers mux, mix, gain configuration, etc., do not
use the auto-increment mode. In addition, between two successive writes to these registers, the host should
keep MFP0 (SPI chip select) high for at least 6.25us, to ensure that the register writes have occurred properly.
The TLV320AIC3106 includes the ability to read/write registers continuously, without needing to provide an
address for every register accessed. In SPI mode, a continuous write is executed by transitioning MFP0 (SPI
chip select) low to start the frame, sending the first 8-bit command word to read/write a particular register, and
then sending multiple bytes of register data, intended for the addressed register and those following. A
continuous read is done similarly, with multiple bytes read in from the addressed register and the following
registers on the page. When the MFP0 (SPI chip select) pin is transitioned high again, the frame ends, as does
the continuous read/write operation. A new frame must begin again with a new command word, to start the next
bus transaction.
Note that this continuous read/write operation does not continue past a page boundary. The user should not
attempt to read/write past the end of a page, since this may result in undesirable operation.
I
2
C Slave Device Addresses for MFP1, MFP0 Settings
MFP1
MFP0
Device
Address
0011000
0011001
0011010
0011011
0
0
1
1
0
1
0
1
I
2
C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the
I
2
C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
Instead, the bus wires are pulled HIGH by pull-up resistors, so the bus wires are HIGH when no device is driving
them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver
contention.
Communication on the I
2
C bus always takes place between two devices, one acting as the master and the other
acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction
of the master. Some I
2
C devices can act as masters or slaves, but the TLV320AIC3106 can only act as a slave
device.
An I
2
C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is
transmitted across the I
2
C bus in groups of eight bits. To send a bit on the I
2
C bus, the SDA line is driven to the
appropriate level while SCL is LOW (a LOW on SDA indicates the bit is zero; a HIGH indicates the bit is one).
Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on SCL clocks the SDA bit
into the receivers shift register.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLV320AIC3106IGQER 制造商:Texas Instruments 功能描述:AUD CODEC 2ADC / 2DAC 24BIT 80BGA - Tape and Reel
TLV320AIC3106IRGZR 功能描述:接口—CODEC Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC3106IRGZT 功能描述:接口—CODEC Lo-Pwr Stereo CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC3106IZQE 功能描述:接口—CODEC Low-Power Stereo RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLV320AIC3106IZQER 功能描述:接口—CODEC Low-Power Stereo RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
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