參數(shù)資料
型號(hào)： TLV320AIC10I
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： General-Purpose 3V to 5.5V 16-bit 22-KSPS DSP CODEC
中文描述： 通用3V至5.5V 16位22 kSPS的DSP的解碼器
文件頁(yè)數(shù)： 20/57頁(yè)
文件大?。?/td> 284K
代理商： TLV320AIC10I
2–6
2.1.13 Automatic Cascading Detection (ACD)
The TLV320AIC10’s ACD makes cascade programming easy and supports the operation of up to eight devices in
cascade. See Appendix A for register map description.
MCLK
DIN
DOUT
FS
SCLK
MCLK
DIN
DOUT
FS
SCLK
MCLK
DIN
DOUT
FS
SCLK
Slave 6
Slave 1
Slave 0
Master
SCLK
MCLK
DIN
DOUT
FSD
FSD
FSD
FS
CLKOUT
DX
DR
FSX
FSR
CLKX
CLKR
TMS320C5X
DVDD
FSD
M/S
M/S
M/S
M/S
(or Master Clock Source)
DVDD
1 k
Figure 2–6. Cascading
2.1.14 Low-Power Mode
To select the low-power mode, in which the AIC10 typically consumes 38.6 mW, set bit D7 of control register 2 to 1
and set the sampling rate at 8 ksps.
2.1.15 Event-Monitor Mode
This mode is only available during the register-write cycle, and is enabled by writing 11to bits D6 and D7 of control
register 3. The event monitor mode is provided for applications that need hardware control and monitoring of external
events. By allowing the device to drive the FLAG terminal (set through bit D3 of the control register 3), the host DSP
is capable of system control through the same serial port that connects the device. Along with this control is the
capability of monitoring the value of the ALTIN terminal during a secondary communication cycle. One application
of this function is in monitoring RING DETECT or OFFHOOK DETECT from a phone-answering system. FLAG allows
response to these incoming control signals. Figure 2–7 shows the timing associated with this operating mode.
FS
DOUT
ALTDI
Primary
Secondary
16 bits
NOTE A: When DIN performs a write operation (sets D12 to 0) during secondary communication.
Figure 2–7. Event Monitor Mode Timing
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