參數(shù)資料
型號: TLV320AIC10I
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: General-Purpose 3V to 5.5V 16-bit 22-KSPS DSP CODEC
中文描述: 通用3V至5.5V 16位22 kSPS的DSP的解碼器
文件頁數(shù): 12/57頁
文件大小: 284K
代理商: TLV320AIC10I
1–6
1.6
Definitions and Terminology
Data transfer interval
The time during which data is transferred from DOUT to DIN. The interval is 16 shift clocks and the
data transfer is initiated by the falling edge of the FS signal.
This refers to the input signal and all of the converted representations through the ADC channel, and
the signal through the DAC channel to the analog output. This is in contrast with the purely-digital
software control data.
Primary communication refers to the digital data-transfer interval. Since the device is synchronous,
the signal data words from the ADC channel and to the DAC channel occur simultaneously.
Secondary communication refers to the digital control and configuration data-transfer interval into
DIN, and the register read-data cycle from DOUT. The data transfer occurs when requested by hard-
ware or software.
Serial peripheral interface standard set by Motorola
Frame/pulse sync refers only to the falling edge of the signal FS that initiates the data-transfer inter-
val. The primary FS starts the primary communication, and the secondary FS starts the secondary
communication.
Frame/pulse sync and sampling period is the time between falling edges of successive primary FS
signals and it is always equal to 256xSCLK if the number of cascading devices is less than 5, or 512
xSCLK if the number of cascading devices is greater than 4.
The sampling frequency
ADC channel refers to all signal-processing circuits between the analog input and the digital
conversion result at DOUT.
DAC channel refers to all signal-processing circuits between the digital data word applied to DIN and
the differential output analog signal available at OUTP and OUTM.
A host is any processing system that interfaces to DIN, DOUT, SCLK, FS, and/or MCLK.
Bit position in the primary data word (xx is the bit number).
Bit position in the secondary data word (xx is the bit number).
The alpha character drepresents valid programmed or default data in the control-register format
(see Section 3.2, Secondary Serial Communication) when discussing other data bit portions of the
register.
Programmable gain amplifier
Finite-duration impulse response
Direct configuration serial interface for host control
Signal data
Primary
communication
Secondary
communication
SPI
Frame/pulse sync
Frame/pulse sync and
sampling period
f
s
ADC channel
DAC channel
Host
Dxx
DSxx
d
PGA
FIR
DCSI
1.7
Register Functional Summary
There are five control registers which are used as follows:
Register 0 The no-op register. Addressing register 0 allows secondary-communication request without altering any
other registers.
Register 1 Control register 1. The data in this register has the following functions:
Produce the output flag to indicate a decimator FIR filter overflow (read cycle only)
Enable of general-purpose operational amplifiers A1, A3, and A4
Enable/bypass ADC’s analog antialiasing filter
Select normal or auxiliary analog input
Control 16-bit or (15+1)-bit mode of DAC operation
Enable/bypass the decimator FIR filter
Enable/bypass the interpolator FIR filter
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