參數(shù)資料
型號(hào)： TLC34076M-135
廠商： Texas Instruments, Inc.
英文描述： Color-Palette(135MHz,與TLC34075兼容，另具24位和16位真彩色模式)
中文描述： 顏色調(diào)色板（135MHz，與TLC34075兼容，另具24位和16位真彩色模式）
文件頁(yè)數(shù)： 20/57頁(yè)
文件大?。?/td> 456K
代理商： TLC34076M-135
SCLK
BITS
2. . . 0
divide dot clock by
BITS
5. . .3
VCLK
divide
dot clock by
2–4
Table 2–4. Output-Clock-Selection-Register Format
BITS
FUNCTION
5
0
4
0
3
0
2
X
1
X
0
X
VCLK frequency = dot-clock frequency
0
0
1
X
X
X
VCLK frequency = dot-clock frequency/2
0
1
0
X
X
X
VCLK frequency = dot-clock frequency/4
0
1
1
X
X
X
VCLK frequency = dot-clock frequency/8
1
0
0
X
X
X
VCLK frequency = dot-clock frequency/16
1
0
1
X
X
X
VCLK frequency = dot-clock frequency/32
VCLK output held at logic high level (default condition)§
1
1
X
X
X
X
X
X
X
0
0
0
SCLK frequency = dot-clock frequency
X
X
X
0
0
1
SCLK frequency = dot-clock frequency/2
X
X
X
0
1
0
SCLK frequency = dot-clock frequency/4
X
X
X
0
1
1
SCLK frequency = dot-clock frequency/8
X
X
X
1
0
0
SCLK frequency = dot-clock frequency/16
X
X
X
1
0
1
SCLK frequency = dot-clock frequency/32
SCLK output held at logic level low (default condition)§
X
X
X
1
1
X
Register bits 6 and 7 are don’t carebits.
When the clock selection is altered, a minimum 30-ns delay is incurred before the new clocks are stabilized
and running
§These lines indicate the power-up conditions required to support the VGA pass-through mode.
Table 2–5. VCLK/SCLK Divide Ratio Selection
(Output-Clock-Selection-Register Value in Hex)
000
001
010
011
100
101
1
2
4
8
16
32
000
1
00
01
02
03
04
05
001
010
2
4
08
10
09
11
0A
12
0B
13
0C
14
0D
15
011
8
18
19
1A
1B
1C
1D
100
16
20
21
22
23
24
25
101
32
28
29
2A
2B
2C
2D
Output-clock-selection register bits
2.3.1
Data is latched inside the device on the rising edge of LOAD, which is basically the same as SCLK but not
disabled during the BLANK active period. Therefore, SCLK must be set as a function of the pixel bus width
and the number of bit planes. SCLK can be selected as divisions of 1, 2, 4, 8, 16, or 32 of the dot clock. If
SCLK is not used, the output is switched off and held low to protect against VRAM lock up due to invalid
SCLK frequencies. SCLK is also held low during the BLANK active period. The SCLK control timing has
been designed to interface directly with the external system VRAM. The shift register in the system VRAM
should be updated during the BLANK-active period. This allows the first SCLK out of BLANK to clock the
VRAM and enable the first group of pixel data to appear on the pixel bus as well as at the TLC34076M pixel
input port. The second SCLK after BLANK latches the first group of pixel port data into the TLC34076M (see
Figure 2–2).
SCLK
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