- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385929 > TLC34076M-135 (Texas Instruments, Inc.) Color-Palette(135MHz,與TLC34075兼容，另具24位和16位真彩色模式) PDF資料下載
參數(shù)資料
| 型號： | TLC34076M-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(135MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（135MHz，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 19/57頁 |
| 文件大?。?/td> | 456K |
| 代理商： | TLC34076M-135 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁
2–3
video rates up to 135 MHz. The dual-mode clock input (ECL/TTL) is primarily an ECL input but can be used
as a TTL-compatible input if the input-clock selection register is so programmed. The clock source used at
power up is CLK0; an alternative source can be selected by software during normal operation. This chosen
clock input is used unmodified as the dot clock (representing the pixel rate to the monitor). The device does
allow for user programming of the SCLK and VCLK outputs (shift and video clocks) via the output-
clock-selection register. The input-/output-clock-selection registers are shown in Tables 2–3, 2–4, and 2–5.
The ECL input can be used as a differential or single-ended input. If the CLK3 input is used as a single-ended
ECL input, the CLK3 input must be externally terminated to set the input common-mode signal level. This
can be done with a simple resistor divider, as is the case with fully differential ECL.
SCLK is designed to drive the VRAMs directly, and VCLK is designed to work with video control signals like
BLANK and SYNC. While SCLK and VCLK are designed as general-purpose shift clock and video clock,
respectively, they also interface directly with the TMS340x0 GSP family directly. Even though SCLK and
VCLK can be selected independently, there is still a relationship between the two. Many system
considerations have been carefully covered in the design, allowing maximum user freedom.
Internally, both SCLK and VCLK are generated from a common clock counter that increments on the rising
edge of the dot clock. Therefore, when VCLK is enabled, it is in phase with SCLK (see Figure 2–1).
The internal clock counter is initialized to value 0 any time the output-clock-selection register (bits 5, 4, 2,
1) are all set to 1s. This provides a simple mechanism to synchronize multiple video interface palettes by
providing a known phase relationship for the various system clocks. One can write directly to the output-
clock-selection register to cause this to occur or any of the various resets (POR, hardware, software–see
section 1.5) also causes the appropriate bits to be written and the counters to reset. It is up to the user to
provide some means of disabling the dot-clock input to the part while this reset is occurring if multiple parts
are to be synchronized.
Appendix A discusses the SCLK/VCLK relationship specific to the TMS340x0 GSP.
as an example)
(dot clock/2
SCLK
as an example)
(dot clock/4
VCLK
Dot Clock
Figure 2–1. Dot Clock/VCLK/SCLK Relationship
Table 2–3. Input-Clock-Selection Register Format
BITS
2
FUNCTION
3
1
0
0
0
0
0
Select CLK0 as clock source§
0
0
0
1
Select CLK1 as clock source
0
0
1
0
Select CLK2 as clock source
0
0
1
1
Select CLK3 as TTL clock source
0
1
0
0
Select CLK3 as TTL clock source
1
0
0
0
Select CLK3 and CLK3 as ECL clock sources
Register bits 4, 5, 6, and 7 are don’t care bits.
When the clock selection is altered, a minimum 30-ns delay is incurred before the
new clocks are stabilized and running.
§CLK0 is chosen at power up to support the VGA pass-through mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLC4501(中文) | Self-Calibrating Dual Operational Amplifier(先進LINEPIC，自校準精密運放) |
| TLC4502(中文) | Self-Calibrating Operational Amplifier(先進LINEPIC，雙組自校準精密運放) |
| TLC540(中文) | 8-Bit Analog-To-Digital Converters With Serial Control And 11 Inputs(串行控制，75ksps,12通道，8位ADC) |
| TLC541(中文) | 8-Bit Analog-To-Digital Converters With Serial Control And 11 Inputs(串行控制，40ksps,12通道，8位ADC) |
| TLC540I | MOSFET N-CH 100V 41A TO-247AC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC34077 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette Data Manual |
| TLC34077135FN | 制造商:TI 功能描述:* |
| TLC352 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:LinCMOSE DUAL DIFFERENTIAL COMPARATOR |
| TLC352CD | 功能描述:校驗器 IC Dual Differential RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時間: 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
| TLC352CDG4 | 功能描述:校驗器 IC Dual Low Vltg LinCMOS Differential RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時間: 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。