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參數(shù)資料
| 型號： | TLC34076M-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(135MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（135MHz，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 15/57頁 |
| 文件大?。?/td> | 456K |
| 代理商： | TLC34076M-135 |
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1–7
1.5
Ordering Information
TLC34076
–
135
M
GA
Pixel clock frequency indicator
MUST CONTAIN TWO OR THREE CHARACTERS:
–135:
135-MHz pixel clock
Military
Package
MUST CONTAIN TWO LETTERS:
GA: 84-pin (12
×
12) grid array
1.6
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
BLANK,
VGABLANK
I
Blanking inputs. Two blanking inputs are provided in order to remove any external multiplexing
of the signals that may cause data and blank to skew. When the VGA pass-through mode is
set in the muxtiplex-control register, VGABLANK is used for blanking; otherwise, BLANK is
used.
CLK<0:2>
I
Dot-clock inputs. Any of the three clocks can be used to drive the dot clock at frequencies up
to 135 MHz. When VGA pass-through mode is active, CLK0 is used by default.
CLK3, CLK3
I
Dual-mode dot-clock input. This input is an ECL-compatible input, but a TTL clock may be used
on either CLK3 or CLK3 if so selected in the input-clock-selection register. This input can be
selected as the dot clock for any frequency of operation up to the device limit. It can also be
used with a single-ended ECL clock source if the unused input is externally terminated to
provide the proper common-mode level.
COMP
I
Compensation input. This terminal provides compensation for the internal reference amplifier.
A resistor (optional) and ceramic capacitor are required between this terminal and VDD. The
resistor and capacitor must be as close to the device as possible to avoid noise pickup. Refer
to Appendix B for more details.
D<0:7>
I/O
MPU interface data bus. Used to transfer data in and out of the register map and palette/overlay
RAM.
FS ADJUST
I
Full-scale adjustment input. A resistor connected between this terminal and GND controls the
full-scale range of the DACs.
GND
Ground. All GND terminals must be connected. The analog and digital GND pins are
connected internally.
HSYNCOUT,
VSYNCOUT
O
Horizontal and vertical sync outputs of the true/complement gate mentioned in the HSYNC,
VSYNC description (see Section 2.8).
HSYNC,
VSYNC
I
Horizontal and vertical sync inputs. HSYNC and VSYNC are used to generate the sync level
on the green current output. They are active-low inputs for the normal modes and are passed
through a true/complement gate. For the VGA pass-through mode, they are passed through
to HSYNCOUT and VSYNCOUT without polarity change as specified by the control register
(see Section 2.8).
IOR, IOG, IOB
O
Analog current outputs. These outputs can drive a 37.5-
load directly (doubly terminated
75-
line), thus eliminating the need for any external buffering.
MUXOUT
O
Multiplex-output control. MUXOUT is software programmable. It is set low to indicate to
external devices that the VGA pass-through mode is being used when the multiplex-control
register value is set to 2Dh. If bit 7 of the general-control register is set high after the mode is
set, this output goes high. MUXOUT is only used for external control; it affects no internal
circuitry.
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