參數(shù)資料
型號(hào)： TLC34076M-135
廠商： Texas Instruments, Inc.
英文描述： Color-Palette(135MHz,與TLC34075兼容，另具24位和16位真彩色模式)
中文描述： 顏色調(diào)色板（135MHz，與TLC34075兼容，另具24位和16位真彩色模式）
文件頁(yè)數(shù)： 16/57頁(yè)
文件大?。?/td> 456K
代理商： TLC34076M-135
1–8
TERMINAL
NAME
I/O
DESCRIPTION
P<0:31>
I
Pixel-input port. This port can be used in various modes as shown in the multiplex-control
register. It is recommended that unused pins be tied to GND. It also supports little-/big-endian
data formats. All the unused terminals must be tied to GND.
RD
I
Read-strobe input. A low logic level on this terminal initiates a read from the TLC34076M
register map. Reads are performed asynchronously and are initiated on the falling edge of RD
(see Figure 3–1).
RS<0:3>
I
Register-select inputs. These terminals specify the location in the register map that is to be
accessed, as shown in Table 2–1.
SCLK
O
Shift-clock output. SCLK is selected as a submultiple of the dot-clock input. SCLK is gated off
during blanking.
SFLAG/
NFLAG
I
Split shift-register-transfer flag or nibble-flag input. SFLAG/NFLAG has two functions. When
the general-control register bit 3 = 0 and bit 2 = 1, split shift-register-transfer function is enabled
and a low-to-high transition on this terminal during a blank sequence initiates an extra SCLK
cycle to allow a split shift-register transfer in the VRAMs. When the general-control register
bit 3 = 1 and bit 2 = 0, a special nibble mode is enabled and this input is sampled at the falling
edge of VCLK. A high value sampled indicates that the next SCLK rising edge should latch the
high nibble of each byte of the pixel data bus; a low value sampled indicates that the low nibble
of each byte of the pixel data bus should be latched (see Section 2.9). When the general-control
register bit 3 = 0 and bit 2 = 0, this terminal is ignored. The condition of bit 3 = 1, bit 2 = 1 is not
allowed, and device operation is unpredictable if they are so set.
Video-clock output. User-programmable output for synchronization of the TLC34076M to a
graphics processor.
VCLK
O
VDD
DVDD
VGA<0:7>
Supply voltage. All VDD terminals must be connected. The analog and digital VDD terminals
are connected internally.
I
VGA pass-through bus. This bus can be selected as the pixel bus for VGA pass-through mode.
It does not allow for any multiplexing.
Vref
Voltage reference for DACs. An internal voltage reference of nominally 1.235 V is supplied. A
0.1-
μ
F ceramic capacitor between this terminal and GND is recommended for noise filtering
using either the internal or an external reference voltage. The internal reference voltage can
be overridden by an externally supplied voltage. The typical connection is shown in
Appendix B.
Write-strobe input. A low logic level on this terminal initiates a write to the TLC34076M register
map. Write transfers are asynchronous. The data written to the register map is latched on the
rising edge of WR (see Figure 3–1).
WR
I
8/6
I
DAC resolution selection input. 8/6 is used to select the data bus width (8 or 6 bits) for the DACs
and is provided to maintain compatibility with the INMOS IMSG176/8 color palette. When this
terminal is at a high logic level, 8-bit bus transfers are used with D<7> the MSB and D<0> the
LSB. For 6-bit bus operation, while the color palette still has the 8-bit information, D<5> shifts
to the bit 7 position, D<0> shifts to the bit 2 position, and the two LSBs are filled with zeros at
the output multiplexer to the DAC. When read in the 6-bit mode, the palette-holding register
zeroes out the two MSBs.
1. Although leaving unused terminals floating does not adversely affect device operation, tying unused
terminals to GND lowers power consumption and thus is recommended.
2. All digital inputs and outputs are TTL compatible, unless otherwise noted.
NOTES:
相關(guān)PDF資料
PDF描述
TLC4501(中文) Self-Calibrating Dual Operational Amplifier(先進(jìn)LINEPIC，自校準(zhǔn)精密運(yùn)放)
TLC4502(中文) Self-Calibrating Operational Amplifier(先進(jìn)LINEPIC，雙組自校準(zhǔn)精密運(yùn)放)
TLC540(中文) 8-Bit Analog-To-Digital Converters With Serial Control And 11 Inputs(串行控制，75ksps,12通道，8位ADC)
TLC541(中文) 8-Bit Analog-To-Digital Converters With Serial Control And 11 Inputs(串行控制，40ksps,12通道，8位ADC)
TLC540I MOSFET N-CH 100V 41A TO-247AC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLC34077 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette Data Manual
TLC34077135FN 制造商:TI 功能描述:*
TLC352 制造商:TI 制造商全稱:Texas Instruments 功能描述:LinCMOSE DUAL DIFFERENTIAL COMPARATOR
TLC352CD 功能描述:校驗(yàn)器 IC Dual Differential RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時(shí)間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel
TLC352CDG4 功能描述:校驗(yàn)器 IC Dual Low Vltg LinCMOS Differential RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類型: 通道數(shù)量: 輸出類型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時(shí)間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*