參數(shù)資料
型號: THS8083CPZP
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: POWER, THERMALLY ENHANCED, PLASTIC, TQFP-100
文件頁數(shù): 38/61頁
文件大?。?/td> 266K
代理商: THS8083CPZP
4–3
4.3
Timing Diagram – 48-Bit Interleaved Mode
This mode allows a double-pixel width output interface with a 1 sampling clock period time offset between buses A
and B. The DATACLK1 output is at half of the sampling clock frequency.
DATACLK
CH1_OUTA[7..0]
CH2_OUTA[7..0]
CH2_OUTB[7..0]
CH1_OUTB[7..0]
CH3_OUTA[7..0]
CH3_OUTB[7..0]
HS
pix 01
01
03
02
04
pix 02
ADCCLK2
DHS
01
03
04
01
03
02
04
02
tPLH(OE)
tPHL(OE)
tsu(DHS)
th(DHS)
tsu(OUT)
th(OUT)
tsu(OUT)
th(OUT)
(DHS_POL = 0
Assumed-Inverted
Polarity Otherwise)
OE
7 ADCCLK2 Cycles Latency
Last Samples From Previous Line
<DHS_MODE> = 1 –> Width
Equal to Width of HS Input
<DHS_MODE> = 0 –> DHS
Width is 1 ADCCLK2 Period
7 ADCCLK2
Cycles Latency
相關(guān)PDF資料
PDF描述
THS8133ACPHP PARALLEL, WORD INPUT LOADING, 0.005 us SETTLING TIME, 10-BIT DAC, PQFP48
THS8133BCPHP PARALLEL, WORD INPUT LOADING, 0.005 us SETTLING TIME, 10-BIT DAC, PQFP48
THS8133BCPHPG4 PARALLEL, WORD INPUT LOADING, 0.005 us SETTLING TIME, 10-BIT DAC, PQFP48
THS8133CPHP PARALLEL, WORD INPUT LOADING, 0.005 us SETTLING TIME, 10-BIT DAC, PQFP48
THS8134BCPHP PARALLEL, 8 BITS INPUT LOADING, 0.005 us SETTLING TIME, 8-BIT DAC, PQFP48
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