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參數(shù)資料
| 型號： | THC63LVD104S |
| 廠商： | THine Electronics, Inc. |
| 英文描述： | 112MHz 30Bits Color LVDS Receiver |
| 中文描述： | 112MHz的30Bits顏色LVDS接收器 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 154K |
| 代理商： | THC63LVD104S |
Copyright 2004 THine Electronics, Inc. All rights reserved 3
THine Electronics, Inc.
THC63LVD104S Rev.1.0
Pin Description
Pin Name
Pin No.
I/O Type
Description
RA+, RA-
50, 49
LVDS IN
LVDS Data In.
RB+, RB-
52, 51
LVDS IN
RC+, RC-
55, 54
LVDS IN
RD+, RD-
60, 59
LVDS IN
RE+,RE-
62, 61
LVDS IN
RCLK+, RCLK-
57, 56
LVDS IN
LVDS Clock In.
RA6 ~ RA0
40,41,42,43,45,46,47
OUT
CMOS/TTL Data Outputs.
RB6 ~ RB0
32,33,34,35,36,38,39
OUT
RC6 ~ RC0
22,24,25,26,27,28,29
OUT
RD6 ~ RD0
14,15,17,18,19,20,21
OUT
RE6 ~ RE0
6,7,8,10,11,12,13
OUT
PD
3
IN
Power down and Output Control.(Table1)
H: Normal operation
L: Power down
OE
4
IN
Output Enable. See Table1.
H:Output enable.
L:Output disable
DK
2
IN
( 3-Level )
Output Clock Delay Timing Select.(Fig5)
t
RCP
=Output Clock Cycle
L: Offset 0[nsec]
M: Offset -
(typ) [nsec]
H: Offset +
(typ)[nsec]
R/F
5
IN
Output Clock Triggering Edge Select.(Fig5)
H: Rising Edge
L: Falling Edge
VCC
9,23,37,48
Power
Power Supply Pins for TTL outputs and digital
circuitry.
CLKOUT
31
OUT
Clock out.
GND
1,16,30,44
Ground
Ground Pins for TTL outputs and digital circuitry.
LVCC
53
Power
Power Supply Pin for LVDS inputs.
LGND
58
Ground
Ground Pin for LVDS inputs.
PVCC
64
Power
Power Supply Pin for PLL circuitry.
PGND
63
Ground
Ground Pin for PLL circuitry.
3
t14
3
t14
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