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THC63LVDF84B/THC63LVDF64B_Rev2.0
Copyright 2001-2003 THine Electronics, Inc. All rights reserved 1
THine Electronics, Inc.
THC63LVDF84B/THC63LVDF64B
LVDS 24Bit/18Bit COLOR HOST-LCD PANEL INTERFACE RECEIVER
General Description
The THC63LVDF84B/THC63LVDF64B receiver sup-
ports wide VCC range(2.5~3.6V). At single 2.5V sup-
ply, the THC63LVDF84B/THC63LVDF64B reduces
EMI and power consumption.
The THC63LVDF84B receiver convert the four
LVDS(Low Voltage Differential Signaling) data streams
back into 28bits of CMOS/TTL data with falling edge
clock.
At a transmit clock frequency of 85MHz, 28bits of RGB
data and 4bits of LCD timing and control data
(HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at
a rate of 2.3Gbps.
Also the THC63LVDF64B receiver convert the three
LVDS data streams back into 21bits of CMOS/TTL data
with falling edge clock.
At a transmit clock frequency of 85MHz, 21bits of RGB
data and 4bits of LCD timing and control data
(HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at
a rate of 1.78Gbps.
Features
Wide VCC range: 2.5~3.6V
Wide dot clock range: 20-85MHz suited for VGA,
SVGA, XGA and SXGA (VCC=3.0~3.6V)
Wide dot clock range: 20-70MHz suited for VGA,
SVGA, XGA and SXGA (VCC=2.5V~3.6V)
PLL requires No external components
Rx power consumption < 80mW @VCC 2.5V,
65MHz Grayscale
Power-Down Mode
Low profile 56 Lead or 48 Lead TSSOP Package
Pin compatible with THC63LVDF84A/F64A
Block Diagram
L
PLL
RA +/-
RB +/-
RC +/-
RD +/-
RCLK +/-
/PDWN
RA0-6
RC0-6
RD0-6
RECEIVER
CLOCK OUT
(20 to 85MHz)
CMOS/TTL
OUTPUT
RB0-6
CLOCK
(LVDS)
20 to 85MHz
DATA
(LVDS)
(140-595Mbit/On Each LVDS Channel)
7
7
7
7
L
PLL
RA +/-
RB +/-
RC +/-
RCLK +/-
/PDWN
RA0-6
RC0-6
RECEIVER
CLOCK OUT
(20 to 85MHz)
CMOS/TTL
OUTPUT
RB0-6
CLOCK
(LVDS)
20 to 85MHz
DATA
(LVDS)
7
7
7
THC63LVDF64B
THC63LVDF84B