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參數(shù)資料
| 型號(hào)： | THC63LVDM63R |
| 廠商： | THine Electronics, Inc. |
| 英文描述： | REDUCED SWING LVDS 24Bit/18Bit COLOR HOST-LCD PANEL INTERFACE |
| 中文描述： | 低擺幅的LVDS 24Bit/18Bit主機(jī)彩色液晶顯示器面板界面 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 203K |
| 代理商： | THC63LVDM63R |
THC63LVDM83R/THC63LVDM63R_Rev2.0
Copyright 2001-2003 THine Electronics, Inc. All rights reserved 1
THine Electronics, Inc.
THC63LVDM83R/THC63LVDM63R
REDUCED SWING LVDS 24Bit/18Bit COLOR HOST-LCD PANEL INTERFACE
General Description
The THC63LVDM83R transmitter converts 28bits of
CMOS/TTL data into LVDS (Low Voltage Differential
Signaling) data stream. A phase-locked transmit clock
is transmitted in parallel with the data streams over a
fifth LVDS link. At a transmit clock frequency of
85MHz, 28bits of RGB data and 4bits of LCD timing
and control data (HSYNC, VSYNC, CNTL1, CNTL2)
are transmitted at a rate of 595Mbps per LVDS channel.
Also available is THC63LVDM63R that converts 21bits
of CMOS/TTL data into LVDS(Low Voltage Differen-
tial Signaling) data stream. Both transmitters can be
programmed reduced swing LVDS through a dedicated
pin for low power consumption and EMI.
Features
28:4 Data channel compression at up to
298 Megabytes per sec throughput
Wide dot clock range: 20-85MHz suited for VGA,
SVGA, XGA and SXGA
Narrow bus (10 lines or 8 lines) reduces cable size
Support Reduced swing LVDS for Low EMI
200mV swing LVDS/350mV swing LVDS
selectable
Support Spread Spectrum Clock Generator
On chip Input Jitter Filtering
PLL requires No external components
Single 3.3V supply with 125mW(TYP)
Power-Down Mode
Low profile 56 or 48 Lead TSSOP Package
Clock Edge Programmable
Improved Replacement for the National DS90C383
or DS90C363
Block Diagram
T
PLL
TA +/-
TB +/-
TC +/-
TD +/-
TCLK +/-
R/F
/PDWN
TA0-6
TC0-6
TD0-6
TRANSMITTER
CLOCK IN
(20 to 85MHz)
CMOS/TTL
INPUTS
7
7
RS
7
TB0-6
7
CLOCK
(LVDS)
20-85MHz
DATA
(LVDS)
(140-595Mbit/On Each
LVDS Channel)
T
PLL
7
7
7
CMOS/TTL
INPUTS
TA0-6
TB0-6
TC0-6
TRANSMITTER
CLOCK IN
(20 to 85MHz)
R/F
/PDWN
RS
TA +/-
TB +/-
TC +/-
TCLK +/-
CLOCK
(LVDS)
20-85MHz
(140-595Mbit/On Each
LVDS Channel)
THC63LVDM83R
THC63LVDM63R
DATA
(LVDS)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| THC63LVDM83C-5S | 制造商:THine Electronics Inc 功能描述:Tray |
| THC63LVDM83D | 制造商:THine Electronics Inc 功能描述: |
| THC63LVDM83E | 制造商:THine Electronics Inc 功能描述:Tray |
| THC63LVDM83R | 制造商:THine Electronics Inc 功能描述:IC,REDUCED SWING LVDS 24BIT COLOR HOST-LCD PANEL INTERFACE,TSSOP,56PIN,PLASTIC |
| THC63LVDM87 | 制造商:THine Electronics Inc 功能描述:Bulk |
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