參數(shù)資料
型號： TFP6422PAP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, THERMALLY ENHANCED, POWER, PLASTIC, TQFP-64
文件頁數(shù)： 56/65頁
文件大?。?/td> 813K
代理商： TFP6422PAP
TFP6422, TFP6424
PanelBus
DIGITAL TRANSMITTER/VIDEO ENCODER COMBO
SLDS118 – MARCH 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
POWER
RAIL
NO.
I/O
DESCRIPTION
Analog Video Out
CVBS
AVCC
40
A
Analog composite video output
Y/G
AVCC
41
A
Analog luminance video output
Analog green output
C/R/Pr
AVCC
43
A
Analog chrominance output
Analog red output
Analog Pr output
B/Pb
AVCC
44
A
Analog blue output
Component Pb output
COMP
AVCC
38
A
Compensation for the internal reference amplifier A 0.1
F capacitor should be connected
between this pin and AVCC.
AFADJ
AVCC
39
A
Full scale adjust control. A 920-
resistor should be connected between this pin and AVSS to
control the full-scale output current on the analog outputs.
I2C Interface and Miscellaneous
SCL
DVCC
15
I/O
I2C serial clock input maximum. Clock rate of 400 kHz. Open drained I/O.
SDA
DVCC
14
I/O
I2C Serial data line open drained I/O.
RST
DVCC
13
I
Reset signal active low.
HTPLG
DVCC
11
I
DVI/P&D/DFP hot plug detect input
A0
DVCC
10
I
I2C
slave address select
HS/CS/GPIO1
AVCC
45
I/O
This signal is only active when RGB analog output is enabled.
Digital horizontal sync output – This is the HSYNC signal that connects to the VGA connector.
Digital composite sync output – Composite HSYNC and VSYNC. The polarity of this signal is
programmable when used for HS/CS.
General-purpose I/O #1 – Second general–purpose I/O. This pin has an internal weak
pull–down of 1 M
(TBD). With GPIO1 as an input, use an external 10 k resistor to pull up or
down to set the state of this pin.
VS/FID
AVCC
46
O
Digital vertical sync output
When the analog RGB video output is enabled this signal is the VSYNC that connects to the
VGA connector.
Digital field ID
When the analog video output is interlaced (composite video, S–video, or interlaced
component video), this signal indicates if the current field is ODD (first field) or EVEN (second
field).
The polarity of this signal is programmable.
GPIO0
DVCC
18
I/O
General-purpose I/O #0
First general–purpose I/O. This pin has an internal weak pull-down of 1 M
(TBD). With
GPIO0 as an input, use an external 10 k
resistor to pull up or down to set the state of this pin.
TEST
DVCC
17
I
Test Mode Enable
This pin must be tied to LOW for normal mode of operation. Connecting this pin to HIGH puts
TFP6422/6424 in test mode.
Digital Video Input Port Voltage Reference
VREF
DVDDQ/2
3
A
Digital video input port voltage reference. – Sets the switching threshold of all the signals listed
in Digital Video Input Port section of this table. VREF must be set to DVDDQ/2, where DVDDQ
is the swing of the signals. DVDDQ ranges from 1.1 V to 1.8 V.
PRODUCT
PREVIEW
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