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參數(shù)資料
| 型號(hào)： | TFP6422PAP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, THERMALLY ENHANCED, POWER, PLASTIC, TQFP-64 |
| 文件頁(yè)數(shù)： | 33/65頁(yè) |
| 文件大?。?/td> | 813K |
| 代理商： | TFP6422PAP |
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TFP6422, TFP6424
PanelBus
DIGITAL TRANSMITTER/VIDEO ENCODER COMBO
SLDS118 – MARCH 2000
39
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
CLK_CTRL
Subaddress = 3B
Default = 0xAA
7
6
5
4
3
2
1
0
CKINDSK[3:0]
CKENCSE
Video encoder core clock select
0
The clock signal generated by the on-chip clock generator PLL_Y is selected
to encode the video
1(*) CLKIN is selected to encode the video
CKINDSK
[3:0]
CLKIN deskew control
0000 –8 T
0001 –7 T
0010 –6 T
0011 –5 T
0100 –4 T
0101 –3 T
0110 –2 T
0111 –T
1000(*) No Skew
1001 T
1010 2 T
1011 3 T
1100 4 T
1101 5 T
1110 6 T
1111 7 T
Where T = approximately 100 ps.
VIDOUT_CTRL
Subaddress = 3C
Default = 0x00/01
7
6
5
4
3
2
1
0
VIDOUT[3:0]
Video output mode
0000(*)
DVI
0001(*)
Simultaneous composite and S–video
0010
Composite video
0011
S–video
0100
Interlaced YPrPb component video (525 or 625 lines)
0101
SCART (Simultaneous composite and interlaced RGB)
0110
Progressive RGB
0111
Simultaneous composite and interlaced YPrPb component video
1000
DACs connection testWrite 1000 to test the connection of four DACs. Read the
connection status for each DAC from DACCON[3:0] bits in CON_STATUS
register. See CON_STATUS for details.
1001–1110 Reserved
1111
Power down
VIDOUT[2:0] defaults to 0000 after reset if INT0# pin is pulled high or defaults to 0001 if INT0 pin
is pulled low during reset.
I2C interface continues to be active in power down modes.
PRODUCT
PREVIEW
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