參數(shù)資料
型號(hào): TEA5766UK
廠商: ST-ERICSSON
元件分類: 接收器
英文描述: FM, AUDIO SINGLE CHIP RECEIVER, PBGA25
封裝: 3.30 X 3.25 MM, 0.60 MM HEIGHT, WLCSP-25
文件頁數(shù): 22/60頁
文件大?。?/td> 298K
代理商: TEA5766UK
TEA5766UK_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 22 March 2007
28 of 59
NXP Semiconductors
TEA5766UK
Stereo FM radio + RDS
9.4.2 Modied Mobile Broadcast Service (MMBS) mode
There are three synchronization modes, RDS, RBDS and MMBS.
RDS mode: the decoder can read A, B, C and D blocks and synchronize on A, B, C
and D blocks.
RBDS mode: the decoder can read A, B, C, D and E blocks and synchronize on A, B,
C and D blocks.
MMBS mode: the decoder can read A, B, C, D and E blocks and synchronize on A, B,
C, D and E blocks.
MMBS mode can be selected using bit MMBS in register TESTREG (see Table 19).
9.4.3 Data overow
During synchronization after RDS data is read from the registers, new available blocks are
shifted to the registers as described in Section 9.1 to Section 9.3. When the registers are
not read in time, the decoder cannot shift any new available block to the registers and
hence a data overow will occur; this is indicated by the DOVF bit which is set to logic 1.
The DOVF bit is reset by a read of the registers or if NWSY = 1 which results in the start of
a new synchronization search.
9.5 RDS ag behavior during read action
Each time when an RDS data block is decoded the DAVN signal will go LOW to signal the
presence of a new data block. Also the DAVN signal triggers the interrupt output INTX. In
principle the microprocessor must now start reading and must have read all RDS data, so
byte 12R to byte 19R before the arrival of a new RDS data block. In the application there
can be a too large delay between the arrival of a new block and reading this block. This
can have various causes such as a microprocessor which has to start up from Sleep
mode or when polling is used instead of interrupt based read actions. Figure 13 describes
the behavior of the DAVFLG and the DAVN signal when polling, which effectively means
that reading can occur at any moment.
Remark: DAVN sets the INTX one-shot generator when DAVMSK = 1. Unlike INTX,
DAVN is not cleared by a read of the mask register.
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